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\begin{document}
\title{Memory expansions for the Commodore~128}
\author
{
  Marko M\"akel\"a {\tt <Marko.Makela@FTP.FUNET.FI>}
    \and
  Pekka Pessi {\tt <Pekka.Pessi@HUT.FI>}
}
\date
{
  April 17th, 1994\\{}
  [last modified December 22nd, 1999]%
  \footnote
  {
    This document is partially based on Pekka Pessi's two articles
    describing an 256~kB internal memory expansion for the
    Commodore~64. The articles were originally published in the
    largest Nordic and Finnish home computer users' magazine,
    MikroBITTI, in its first two issues in the year 1987. Six years
    later, they were translated to English and edited by Marko M\"akel\"a,
    with help from Pekka Pessi. The translation should be
    available via anonymous FTP from {\tt FTP.FUNET.FI}.
  }
  \footnote
  {
    August 1996: Thanks to Wolfgang Scherr from Austria, who noticed my
    mistake in the schematic diagram.  The inputs of the 74LS153 chip were
    mixed, which caused the address block decoding to fail.
  }
  \footnote
  {
    By now, I know of two Commodore 64 (mine and Pekka Pessi's) where
    this expansion has been built, and of four Commodore 128s (of which
    two expanded by me, and the other two by Wolfgang Scherr and Matthias
    Kirchner from Germany).  The expansion never became a success, although
    the banked concept is technically better than e.g. the Commodore REU.
    Meanwhile, there is one more program that supports the expansion: my
    transfer system prlink.
  }
}

\maketitle

\begin{sl} As the Commodore~128 was first introduced, 128 kilobytes
feeled like an unbelievably big amount of memory. Nowadays even plain
terminals and game consoles have more, and you can easily expand even
a Commodore~64 to 256 kilobytes, twice as much as its big brother has
by default.

There are several commercial memory expansions for the Commodores 128
and 64, but they are rather expensive, and most if not all of them are
not being manufactured any more.

This article introduces three different memory expansions for the
Commodore 128 and 128D computers. With these instructions, you can
expand your computer to 256, 512 or 1024 kilobytes of internal memory.
The 1024 kilobyte expansion is actually a combination of the two
former ones, and it is fully compatible with both of them. When built
by oneself, the 1024~kB expansion can remain cheaper than 200 Finnish
marks.%
\footnote
{
  One Americal dollar (USD) is equivalent to five or six Finnish marks
  (FIM). My expansion costed about 240~FIM, but I bought some parts in
  vain, and could have bought the (second-hand) memory chips somewhat
  cheaper. This time they costed 117~FIM.
}
\end{sl}
\medskip

I set three goals to the expansions. The bigger expansions should be
fully compatible with the internal 256~kB expansion for the
Commodore~64 when the computer is in C64 mode, and the 256~kB and
1024~kB expansions should be downwards compatible with a commercial
internal 256~kB expansion for the Commodore~128. Finally, an expanded
computer should be fully downwards compatible with an unexpanded one.

The design aims to a hardware that supports programming. The 256~kB
and 1~MB expansions enhance the capabilities of the MMU in a way that
the engineers at Commodore must have planned, and the other memory
management logic is even easier to program.

\newpage
\tableofcontents
\newpage

\section{Some basics}

This article describes two memory expansions: an expansion that adds
two new memory banks to the Commodore~128, doubling its memory space,
and another expansion which expands each bank to 256 kilobytes,
quadrupling the memory space. The former is the 256~kB expansion, from
here on the MMU expansion, and the latter is the 512~kB expansion, or
the PIA expansion. Combining these two expansions gives you four banks
of 256 kilobytes each, that is 1024 kilobytes.

When I made the 256~kB expansion to my Commodore~64, I renamed the
computer to 2564 --- 256~kB C64. The first three digits specify the
amount of memory, whereas the last two ones tell the machine type
number. A logical choice for the name of a 512~kB C128 is 5128 --- the
first three digits tell the amount of memory in kilobytes, and the
last three expose the original machine type. Unfortunately the 256~kB
and 1024~kB expansions for the C128 cannot be named so nicely. I have
baptized my C128D to C1028D, though.

The subsections \ref{PIA1} through \ref{PIA4} of this section apply
for the PIA expansion. You can skip them, if you want to save some
trouble and money and are going to expand your machine only to 256
kilobytes. Similarly, the section \ref{MMU} can be skipped if you aim
only to the 512 kilobyte expansion.

\subsection{Expansion memory in 16~kB blocks}
\label{PIA1}

The processor of Commodore~128, MOS~8502, has an 8-bit data bus, and
its address bus is 16 bits wide. Like other 8-bit processors, it can
address only 64~kB of memory at a time. In most 8-bit computers, the
memory is limited to these 64 kilobytes. How could one add memory
above this limit?

The solution is simple: the memory is divided into banks of no more
than 64~kB, which are switched on and off. Some processors have been
added a special circuit for this purpose, in which case the executing
program can be in its own 64~kB bank and the processed data in another
bank. For example, MOS~6509, a fellow processor of MOS~8502, works in
this way, enabling access to one megabyte. The Commodore 128 uses a
sophisticated chip, MOS~8722~MMU (Memory Management Unit), which lets
you to activate one 64~kB memory bank of a total of two memory banks
at a time.

The PIA expansion expands each C128 memory bank to 256 kilobytes. The
extended memory is divided to sixteen blocks of sixteen kilobytes
each. The processor can address up to four of them at a time. Every
four 16~kB segment of the address space can be mapped to any 16~kB
block. Figure~\ref{MemoryMap} shows the mapping right after startup.

However, the video chip VIC-IIe --- MOS~8566\footnote{8564 for NTSC}
--- retrieves its data from the memory outside the normal bus. The
internal address registers of VIC-IIe are 14 bits wide, so it can
address only 16~kB without external logic. The required two extra bits
for accessing the whole 64~kB video bank are provided from the second
CIA chip, and the video bank is selected by the MMU. Our extra logic
provides additional two address bits for accessing the whole 256~kB of
the selected video memory bank.

\begin{figure}
\setlength{\unitlength}{.75ex}
\begin{center}
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% Captions
\put(-10,98){\makebox(20,2){{\bf RAM pool} (bank {\tt 0})}}
\put(-40,98){\makebox(20,2){\bf MPU's RAM}}
\put(20,98){\makebox(20,2){\bf VIC-IIe's RAM}}
% The frames
\thicklines
% Vertical lines
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\put(-40,48){\line(0,1){48}}\put(-20,48){\line(0,1){48}}
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% Horizontal lines
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\multiput(10,0)(0,6){17}{\line(-1,0){5}}
\multiput(-40,48)(0,12){5}{\line(1,0){5}}
\multiput(-20,48)(0,12){5}{\line(-1,0){5}}
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% Vectors
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% Addresses
\put(-5,-1){\makebox(10,2){\tt\$00000}}
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\put(-5,89){\makebox(10,2){\tt\$3C000}}
\put(-5,95){\makebox(10,2){\tt\$40000}}
\put(-35,47){\makebox(10,2){\tt\$0000}}
\put(-35,59){\makebox(10,2){\tt\$4000}}
\put(-35,71){\makebox(10,2){\tt\$8000}}
\put(-35,83){\makebox(10,2){\tt\$C000}}
\put(-35,95){\makebox(10,2){\tt\$10000}}
\put(25,47){\makebox(10,2){\tt\$0000}}
\put(25,59){\makebox(10,2){\tt\$4000}}
\put(25,71){\makebox(10,2){\tt\$8000}}
\put(25,83){\makebox(10,2){\tt\$C000}}
\put(25,95){\makebox(10,2){\tt\$10000}}
% Labels
\put(-10,2){\makebox(20,2){Block \tt 0}}
\put(-10,8){\makebox(20,2){Block \tt 1}}
\put(-10,14){\makebox(20,2){Block \tt 2}}
\put(-10,20){\makebox(20,2){Block \tt 3}}
\put(-10,26){\makebox(20,2){Block \tt 4}}
\put(-10,32){\makebox(20,2){Block \tt 5}}
\put(-10,38){\makebox(20,2){Block \tt 6}}
\put(-10,44){\makebox(20,2){Block \tt 7}}
\put(-10,50){\makebox(20,2){Block \tt 8}}
\put(-10,56){\makebox(20,2){Block \tt 9}}
\put(-10,62){\makebox(20,2){Block \tt A}}
\put(-10,68){\makebox(20,2){Block \tt B}}
\put(-10,74){\makebox(20,2){Block \tt C}}
\put(-10,80){\makebox(20,2){Block \tt D}}
\put(-10,86){\makebox(20,2){Block \tt E}}
\put(-10,92){\makebox(20,2){Block \tt F}}
\multiput(-40,53)(60,0){2}{\makebox(20,2){Segment \tt 0}}
\multiput(-40,65)(60,0){2}{\makebox(20,2){Segment \tt 1}}
\multiput(-40,77)(60,0){2}{\makebox(20,2){Segment \tt 2}}
\multiput(-40,89)(60,0){2}{\makebox(20,2){Segment \tt 3}}
\end{picture}
\end{center}
\caption{Memory mapping right after power-up}
\label{MemoryMap}
\end{figure}

\begin{figure}[hbt]
\setlength{\unitlength}{1.5ex}
\begin{center}
\begin{picture}(50,16)(-5,0)
% Captions
\put(-5,16){\makebox(20,2){\bf 4164}}
\put(25,16){\makebox(20,2){\bf 41256}}
% The Dual-In-Line housings
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% The pins
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\multiput(39,1)(0,2){8}{\line(1,0){1}}
% The pin numbers
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\multiput(6,14)(30,0){2}{\makebox(2,2)[r]{16}}
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\multiput(6,12)(30,0){2}{\makebox(2,2)[r]{15}}
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\multiput(6,10)(30,0){2}{\makebox(2,2)[r]{14}}
\multiput(2,8)(30,0){2}{\makebox(2,2)[l]{4}}
\multiput(6,8)(30,0){2}{\makebox(2,2)[r]{13}}
\multiput(2,6)(30,0){2}{\makebox(2,2)[l]{5}}
\multiput(6,6)(30,0){2}{\makebox(2,2)[r]{12}}
\multiput(2,4)(30,0){2}{\makebox(2,2)[l]{6}}
\multiput(6,4)(30,0){2}{\makebox(2,2)[r]{11}}
\multiput(2,2)(30,0){2}{\makebox(2,2)[l]{7}}
\multiput(6,2)(30,0){2}{\makebox(2,2)[r]{10}}
\multiput(2,0)(30,0){2}{\makebox(2,2)[l]{8}}
\multiput(6,0)(30,0){2}{\makebox(2,2)[r]{9}}
% The descriptions
\put(-5,14){\makebox(5,2)[r]{NC}}
\put(25,14){\makebox(5,2)[r]{MA8}}
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\multiput(-5,12)(30,0){2}{\makebox(5,2)[r]{D}}
\multiput(10,12)(30,0){2}{\makebox(5,2)[l]{\overbar{CAS}}}
\multiput(-5,10)(30,0){2}{\makebox(5,2)[r]{\overbar{W}}}
\multiput(10,10)(30,0){2}{\makebox(5,2)[l]{Q}}
\multiput(-5,8)(30,0){2}{\makebox(5,2)[r]{\overbar{RAS}}}
\multiput(10,8)(30,0){2}{\makebox(5,2)[l]{MA6}}
\multiput(-5,6)(30,0){2}{\makebox(5,2)[r]{MA0}}
\multiput(10,6)(30,0){2}{\makebox(5,2)[l]{MA3}}
\multiput(-5,4)(30,0){2}{\makebox(5,2)[r]{MA2}}
\multiput(10,4)(30,0){2}{\makebox(5,2)[l]{MA4}}
\multiput(-5,2)(30,0){2}{\makebox(5,2)[r]{MA1}}
\multiput(10,2)(30,0){2}{\makebox(5,2)[l]{MA5}}
\multiput(-5,0)(30,0){2}{\makebox(5,2)[r]{$\rm V_{DD}$}}
\multiput(10,0)(30,0){2}{\makebox(5,2)[l]{MA7}}
\end{picture}
\caption{The Dynamic Random Access Memory Chips 4164 and 41256}
\end{center}
\end{figure}

\subsection{Memory chips}
\label{PIA2}

Commodore~128 uses 64~kb dynamic RAM chips of JEDEC standard. In 1982,
when the Commodore~64 was introduced, they were most modern
technology, they needed only one operating voltage supply instead of
traditional three.

The semiconductor memories have developed fast, however, and now a
chip in a DIP of equal size can hold 256 kilobits. The pinout of these
256~kb chips differs minimally from the 64~kb ones. The smaller 64~kb
chips, at least the ones used in C64 and C128, have one unused
contact. The address line to handle three times bigger memory is tied
to this pin. In the DRAMs the address lines are multiplexed: two
address bits use the same pin successively.

In the MikroBITTI article Pekka wrote that 256~kb chips are rather
cheap, and the price would lower as the production rate
increases. Nowadays the production must have almost stopped. When
Pekka bought his chips between March and April of 1986, they costed
about 50~FIM each. When the original article was published, they
costed less than 20~FIM. After that the prices rose due to a memory
shortage. But nowadays the chips don't cost practically anything, if
you're lucky. Many users of IBM~PC compatibles want to upgrade their
system memory with 1~Mb chips or alike and would like to get rid of
their old 256~kb chips. I bought eight second-hand chips with total
35~FIM, and later 36 chips with 117~FIM, including shipping. The
lowest price of unused chip I encountered was 13~FIM a piece and the
highest was 30~FIM, almost 10 times the price I paid!

The 256~kb chips don't consume significantly more power, so there is
no need for a bigger power supply. However, devices that take their
power directly from the computer can cause problems. You can find this
out by experimenting.

The speed of the chips doesn't prevent the replacement either.
According to their schematics diagrams, Commodore 64 and 128 can use
chips with access time of 200~nanoseconds.\footnote{Besides, the oldest
Commodore~64 I have uses 300~ns chips housed in ceramic packages.}
Even the slowest 256~kb dynamic RAMs are not that slow.

It might be wise to replace the bypass capacitors near the memory
chips with bigger ones, at least if you are going to make the MMU
expansion\footnote{See Section \ref{MMU}.}. On the other hand, my
machine works well with the default 220~nF capacitors. If your
computer starts to work unreliably, too small bypass capacitors could
be the culprit.

\subsection{Dynamic headaches}
\label{PIA3}

The dynamic RAM chips are organized in rows and columns. In 64~kb
chips, a row is 256 bits wide, and in 256~kb ones it is 512 bits
wide. Also the memory address is divided into row and column
addresses. When a bit is being accessed in the dynamic RAM, the row
address is asserted before the column address.

First the interfacing circuitry puts the row address on the
Multiplexed Address bus, while the video chip asserts the \overbar{RAS}
(Row Address Select) signal for a short period. After that, the video
chip pulls the MUX line low, and the interfacing circuitry places the
column address on the bus while pulling low the \overbar{CAS} (Column
Address Select) signal of the selected RAM bank. After all this, the
bits in that position can be read or written.

The computer has two circuitries that take care of this
multiplexing. The multiplexers U14 and U15 form the address when
either one of the C128's two processors has the bus, whereas the video
chip produces the row and column addresses itself when it needs its
screen data.

You could access a set of nearby locations faster, if you specified
the row address only once, and then produced only the column addresses
for each location. This technique is supported in the Acorn Archimedes
computer on the processor level, and some other computers utilize it
with external circuitry as memory interleaving. The Commodore,
however, does not have to hassle with this, as its system clock rate
is so slow. As a matter of fact, it actually uses the least
significant processor address bits (A0--A7) as a row address and the
most significant bits (A8--A15) as the column address.

\subsection{Memory refresh}
\label{PIA4}

A dynamic memory chip stores the data bits as charged tiny capacitors,
which discharge among the time. The data must be refreshed
periodically, every 2--4 milliseconds, by recharging the capacitors.

If the whole contents of the memory was refreshed simultaneously, the
power peak would cause enormous problems. Only a block of one or two
rows can be refreshed at a time. The 64~kb chips have 128 blocks to be
refreshed, which implies a 7-bit refresh counter ($2^7$ equals 128).

In order to avoid disturbance, 256~kb chips must have more blocks.
Thus they require a longer refresh counter (8 bits). As the amount of
refresh cycles has increased, the capacitors' ability of keeping
charge has been improved. The 64 kilobit DRAMs required 128 refresh
cycles every 2 milliseconds, now the 256~kb chips need 256 cycles but
every 4~ms.

Whenever you select a row address,\footnote{See Section \ref{PIA3}.}
the block to which the row address belongs gets refreshed. As the 64
kilobit chips have a 7-bit refresh counter, the lowest seven row
address bits specify the row address, and the highest bit is ignored.
The 256 kilobit memory chips have an 8-bit counter, so they ignore the
9th row address bit and determine the block to be refreshed by the
eight lowest bits.

The VIC-IIe chip refreshes the memory systematically, 5 rows in the
end of each screen scan line. It does this by selecting a row address
determined by its internal counter, and then increases this counter by
one. The video chip could have only 7-bit refresh counter, and it
would still operate with 64~kb chips, but fortunately it has an 8-bit
counter, so all of the 256~kb chips get refreshed.

Newer memory chips can be refreshed using a CAS-before-RAS technique.
In this technique, you pull first the \overbar{CAS} signal low, and
then the \overbar{RAS} signal. The memory chips recognize this as a
memory refresh condition, and they refresh a block and increase their
internal refresh counter. However, this technique was not available
when the Commodore~64 and its video chip were designed.

\subsection{The MMU expansion}
\label{MMU}

The Commodore~128 has two memory banks, numbered {\tt 0} and {\tt 1}.
The banks are switched in and out by a custom chip called MOS~8722~MMU
(Memory Management Unit). The chip has the registers for handling four
memory banks, but there are only two hardware lines for bank selection,
named \overbar{CAS0} and \overbar{CAS1}. They are connected to the
\overbar{CAS} signal\footnote{See Section \ref{PIA3}.} of the memory
chips in banks {\tt 0} and {\tt 1}, respectively.

The MMU expansion adds two new memory banks to the computer. It adds
another 8722~MMU chip to the system, routing some signals so that the
chip considers bank~{\tt 2} as bank~{\tt 1}. The \overbar{CAS0} and
\overbar{CAS1} outputs of the two MMU chips will be combined to form
the \overbar{CAS} signals for all four memory banks. The logic glue
involved is very simple, and designing it was quite straight-forward.

\section{Building the expansion}
\subsection{Disclaimer}

Although this procedure worked perfectly for me, I cannot guarantee
that anyone else can perform this upgrade without damaging their
computer. I therefore disclaim any responsibilty for any damage that
may occur as a result of attempting this upgrade. It will also void
any warranty on your computer.

On a more positive note, there is no reason why someone who is
experienced in wielding a soldering iron, and has done some electronic
construction or troubleshooting, should not be able to perform this
upgrade successfully.

\subsection{Getting started}

A termostate soldering iron, desoldering pump or other desoldering
tool, a screwdriver, a spoon and a continuity tester are the only
tools needed. The spoon is for removing the chips. A bottle top
remover is not suitable for that.%
\footnote
{
  A tiny screwdriver is equally good. Just insert the screwdriver tip
  under one end of the chip and wound it a bit in upward angle so that
  the chip moves slightly. Then insert it to the other end of the chip
  and try to lift it a bit. You may have to repeat this procedure. Be
  careful not to wound the pins too much.
}
The continuity tester is vital for checking suspicious connections. If
your tester does not automatically select proper measuring range, use
the coarsest (M$\Omega$) range, as it uses smallest current, which
shouldn't damage any chips on the board.

The installation begins of course by opening the machine and removing
the keyboard and LED cables (and internal drive and power supply in
the C128D). It is useful to memorize, photograph or draw how the parts
were initially connected.

After removing the cables, open the screws that hold the metal RF
shield and the motherboard with the case, and remove the shield and
the board.

If you are going to expand your machine only to 256 kilobytes, skip
the following subsection. If you aim to a whole megabyte, expand your
computer first to 512 kilobytes, and then make the MMU expansion.

\subsection{Expanding to 512 kilobytes}
\label{PIAexpansion}

The PIA expansion consists of one daughter board, which contains most
of the new logic, one piggy-backed chip, and a spaghetti of wires.

In Figure \ref{PIAschematics}, there is a schematics diagram of the
daughter board for the PIA expansion. There are some signals that you
must wire to the mother board. You can take the \overbar{I/O2} and A7
signals from the cartridge port, or from some through-put location near
the daughter board. The \overbar{I/O2} signal should be on the pin~7 of
the chip U3 (74LS138). The A7 can be also taken from the MMU's (U7,
MOS~8722) pin 23, in which case the address range of the PIA will be
limited to {\tt\$DFC0}--{\tt\$DFFF} instead of {\tt\$DF80}--{\tt\$DFFF},
or from the 8502's pin 14. It is also on the multiplexor U14 (74LS257A),
in pin~3.

The MA8 signal is the new Multiplexed Address line for the memory chips
and should be soldered to the pin~1 of each chip. All the remaining five
signals on the right edge of the diagram interface to the multiplexor
chip U14. The MUX signal goes to pin~1. To interface the address lines
A14, A15, B14 and B15, you have to desolder two pins of the multiplexor,
2 and 5. The signal A15 should then be wired to the mother board contact
under the multiplexor pin~2, or to the 8502's pin~23, and the signal B15,
the relocated address line should be soldered to the multiplexor's
pin~2. Similarly, the contacts A14 and B14 should be connected to the
system bus line A14 and the U14's pin~5, respectively. Figure
\ref{U14_pins} shows the pinout of the multiplexor chip U14.

\begin{figure}
\setlength{\unitlength}{1.25ex}
\begin{center}
\begin{picture}(64,62)(0,4)
%
% Captions
%
\put(6.8,46){\makebox(6.4,2){\parbox{8ex}{\center\bf U1 M6526}}}
\put(28,25){\makebox(8,2){\parbox{10ex}{\center\bf IC1 MC6821}}}
\put(51,35){\makebox(4,2){\parbox{5ex}{\center\bf IC2 '153}}}
\put(51,15){\makebox(4,2){\parbox{5ex}{\center\bf IC3 '151}}}
%
% The MOS 6526 CIA
%
%% The frame and the pins
\thicklines
\put(2,12){\line(0,1){42}\line(1,0){16}\line(0,1){42}}\put(2,54){\line(1,0){16}}
\thinlines
\multiput(1,16)(0,2){18}{\line(1,0){1}}
\multiput(18,14)(0,2){20}{\line(1,0){1}}
\put(10,54){\vector(0,1){2}}
\put(9,10){\line(1,0){1}\line(0,1){2}\line(1,0){1}}
%% The pin numbers and the labels
\put(0,50){\makebox(1.75,2)[r]{2}}\put(2.25,49){\makebox(4,2)[l]{PA0}}
\put(0,48){\makebox(1.75,2)[r]{3}}\put(2.25,47){\makebox(4,2)[l]{PA1}}
\put(0,46){\makebox(1.75,2)[r]{4}}\put(2.25,45){\makebox(4,2)[l]{PA2}}
\put(0,44){\makebox(1.75,2)[r]{5}}\put(2.25,43){\makebox(4,2)[l]{PA3}}
\put(0,42){\makebox(1.75,2)[r]{6}}\put(2.25,41){\makebox(4,2)[l]{PA4}}
\put(0,40){\makebox(1.75,2)[r]{7}}\put(2.25,39){\makebox(4,2)[l]{PA5}}
\put(0,38){\makebox(1.75,2)[r]{8}}\put(2.25,37){\makebox(4,2)[l]{PA6}}
\put(0,36){\makebox(1.75,2)[r]{9}}\put(2.25,35){\makebox(4,2)[l]{PA7}}
\put(0,34){\makebox(1.75,2)[r]{10}}\put(2.25,33){\makebox(4,2)[l]{PB0}}
\put(0,32){\makebox(1.75,2)[r]{11}}\put(2.25,31){\makebox(4,2)[l]{PB1}}
\put(0,30){\makebox(1.75,2)[r]{12}}\put(2.25,29){\makebox(4,2)[l]{PB2}}
\put(0,28){\makebox(1.75,2)[r]{13}}\put(2.25,27){\makebox(4,2)[l]{PB3}}
\put(0,26){\makebox(1.75,2)[r]{14}}\put(2.25,25){\makebox(4,2)[l]{PB4}}
\put(0,24){\makebox(1.75,2)[r]{15}}\put(2.25,23){\makebox(4,2)[l]{PB5}}
\put(0,22){\makebox(1.75,2)[r]{16}}\put(2.25,21){\makebox(4,2)[l]{PB6}}
\put(0,20){\makebox(1.75,2)[r]{17}}\put(2.25,19){\makebox(4,2)[l]{PB7}}
\put(0,18){\makebox(1.75,2)[r]{18}}\put(2.25,17){\makebox(4,2)[l]{\overbar{PC}}}
\put(0,16){\makebox(1.75,2)[r]{24}}\put(2.25,15){\makebox(4,2)[l]{\overbar{FLAG}}}
\put(10.25,10){\makebox(2,2)[l]{1}}\put(8,12){\makebox(4,2){$\rm V_{SS}$}}
\put(18.25,14){\makebox(2,2)[l]{19}}\put(14,13){\makebox(3.75,2)[r]{TOD}}
\put(18.25,16){\makebox(2,2)[l]{22}}\put(14,15){\makebox(3.75,2)[r]{R/\overbar{W}}}
\put(18.25,18){\makebox(2,2)[l]{23}}\put(14,17){\makebox(3.75,2)[r]{\overbar{CS}}}
\put(18.25,20){\makebox(2,2)[l]{25}}\put(14,19){\makebox(3.75,2)[r]{$\Phi_2$}}
\put(18.25,22){\makebox(2,2)[l]{26}}\put(14,21){\makebox(3.75,2)[r]{D7}}
\put(18.25,24){\makebox(2,2)[l]{27}}\put(14,23){\makebox(3.75,2)[r]{D6}}
\put(18.25,26){\makebox(2,2)[l]{28}}\put(14,25){\makebox(3.75,2)[r]{D5}}
\put(18.25,28){\makebox(2,2)[l]{29}}\put(14,27){\makebox(3.75,2)[r]{D4}}
\put(18.25,30){\makebox(2,2)[l]{30}}\put(14,29){\makebox(3.75,2)[r]{D3}}
\put(18.25,32){\makebox(2,2)[l]{31}}\put(14,31){\makebox(3.75,2)[r]{D2}}
\put(18.25,34){\makebox(2,2)[l]{32}}\put(14,33){\makebox(3.75,2)[r]{D1}}
\put(18.25,36){\makebox(2,2)[l]{33}}\put(14,35){\makebox(3.75,2)[r]{D0}}
\put(18.25,38){\makebox(2,2)[l]{34}}\put(14,37){\makebox(3.75,2)[r]{\overbar{RESET}}}
\put(18.25,40){\makebox(2,2)[l]{35}}\put(14,39){\makebox(3.75,2)[r]{RS3}}
\put(18.25,42){\makebox(2,2)[l]{36}}\put(14,41){\makebox(3.75,2)[r]{RS2}}
\put(18.25,44){\makebox(2,2)[l]{37}}\put(14,43){\makebox(3.75,2)[r]{RS1}}
\put(18.25,46){\makebox(2,2)[l]{38}}\put(14,45){\makebox(3.75,2)[r]{RS0}}
\put(18.25,48){\makebox(2,2)[l]{21}}\put(14,47){\makebox(3.75,2)[r]{\overbar{IRQ}}}
\put(18.25,50){\makebox(2,2)[l]{39}}\put(14,49){\makebox(3.75,2)[r]{SP}}
\put(18.25,52){\makebox(2,2)[l]{40}}\put(14,51){\makebox(3.75,2)[r]{CNT}}
\put(10.25,54){\makebox(2,2)[l]{20}}\put(8,52){\makebox(4,2){$\rm V_{DD}$}}
%
% The MC 6821 PIA
%
%% The frame and the pins
\thicklines
\put(24,6){\line(0,1){44}\line(1,0){16}\line(0,1){44}}\put(24,50){\line(1,0){16}}
\thinlines
\multiput(20,8)(0,2){2}{\line(1,0){4}}\multiput(23,16)(0,2){16}{\line(1,0){1}}
\multiput(40,8)(0,2){8}{\line(1,0){1}}\multiput(40,26)(0,2){12}{\line(1,0){1}}
\put(32,50){\vector(0,1){2}}
\put(31,4){\line(1,0){1}\line(0,1){2}\line(1,0){1}}
%% The pin numbers and the labels
\put(22,46){\makebox(1.75,2)[r]{36}}\put(24.25,45){\makebox(4,2)[l]{RS0}}
\put(22,44){\makebox(1.75,2)[r]{35}}\put(24.25,43){\makebox(4,2)[l]{RS1}}
\put(22,42){\makebox(1.75,2)[r]{38}}\put(24.25,41){\makebox(4,2)[l]{\overbar{IRQA}}}
\put(22,40){\makebox(1.75,2)[r]{37}}\put(24.25,39){\makebox(4,2)[l]{\overbar{IRQB}}}
\put(22,38){\makebox(1.75,2)[r]{34}}\put(24.25,37){\makebox(4,2)[l]{\overbar{RESET}}}
\put(22,36){\makebox(1.75,2)[r]{33}}\put(24.25,35){\makebox(4,2)[l]{D0}}
\put(22,34){\makebox(1.75,2)[r]{32}}\put(24.25,33){\makebox(4,2)[l]{D1}}
\put(22,32){\makebox(1.75,2)[r]{31}}\put(24.25,31){\makebox(4,2)[l]{D2}}
\put(22,30){\makebox(1.75,2)[r]{30}}\put(24.25,29){\makebox(4,2)[l]{D3}}
\put(22,28){\makebox(1.75,2)[r]{29}}\put(24.25,27){\makebox(4,2)[l]{D4}}
\put(22,26){\makebox(1.75,2)[r]{28}}\put(24.25,25){\makebox(4,2)[l]{D5}}
\put(22,24){\makebox(1.75,2)[r]{27}}\put(24.25,23){\makebox(4,2)[l]{D6}}
\put(22,22){\makebox(1.75,2)[r]{26}}\put(24.25,21){\makebox(4,2)[l]{D7}}
\put(22,20){\makebox(1.75,2)[r]{25}}\put(24.25,19){\makebox(4,2)[l]{E}}
\put(22,18){\makebox(1.75,2)[r]{24}}\put(24.25,17){\makebox(4,2)[l]{CS1}}
\put(22,16){\makebox(1.75,2)[r]{21}}\put(24.25,15){\makebox(4,2)[l]{R/\overbar{W}}}
\put(22,10){\makebox(1.75,2)[r]{22}}\put(24.25,9){\makebox(4,2)[l]{CS0}}
\put(22,8){\makebox(1.75,2)[r]{23}}\put(24.25,7){\makebox(4,2)[l]{\overbar{CS2}}}
\put(32.25,4){\makebox(2,2)[l]{1}}\put(30,6){\makebox(4,2){$\rm V_{SS}$}}
\put(40.25,8){\makebox(2,2)[l]{17}}\put(36,7){\makebox(3.75,2)[r]{PB7}}
\put(40.25,10){\makebox(2,2)[l]{16}}\put(36,9){\makebox(3.75,2)[r]{PB6}}
\put(40.25,12){\makebox(2,2)[l]{13}}\put(36,11){\makebox(3.75,2)[r]{PB3}}
\put(40.25,14){\makebox(2,2)[l]{12}}\put(36,13){\makebox(3.75,2)[r]{PB2}}
\put(40.25,16){\makebox(2,2)[l]{9}}\put(36,15){\makebox(3.75,2)[r]{PA7}}
\put(40.25,18){\makebox(2,2)[l]{8}}\put(36,17){\makebox(3.75,2)[r]{PA6}}
\put(40.25,20){\makebox(2,2)[l]{5}}\put(36,19){\makebox(3.75,2)[r]{PA3}}
\put(40.25,22){\makebox(2,2)[l]{4}}\put(36,21){\makebox(3.75,2)[r]{PA2}}
\put(40.25,26){\makebox(2,2)[l]{19}}\put(36,25){\makebox(3.75,2)[r]{CB2}}
\put(40.25,28){\makebox(2,2)[l]{18}}\put(36,27){\makebox(3.75,2)[r]{CB1}}
\put(40.25,30){\makebox(2,2)[l]{15}}\put(36,29){\makebox(3.75,2)[r]{PB5}}
\put(40.25,32){\makebox(2,2)[l]{14}}\put(36,31){\makebox(3.75,2)[r]{PB4}}
\put(40.25,34){\makebox(2,2)[l]{11}}\put(36,33){\makebox(3.75,2)[r]{PB1}}
\put(40.25,36){\makebox(2,2)[l]{10}}\put(36,35){\makebox(3.75,2)[r]{PB0}}
\put(40.25,38){\makebox(2,2)[l]{7}}\put(36,37){\makebox(3.75,2)[r]{PA5}}
\put(40.25,40){\makebox(2,2)[l]{6}}\put(36,39){\makebox(3.75,2)[r]{PA4}}
\put(40.25,42){\makebox(2,2)[l]{3}}\put(36,41){\makebox(3.75,2)[r]{PA1}}
\put(40.25,44){\makebox(2,2)[l]{2}}\put(36,43){\makebox(3.75,2)[r]{PA0}}
\put(40.25,46){\makebox(2,2)[l]{39}}\put(36,45){\makebox(3.75,2)[r]{CA2}}
\put(40.25,48){\makebox(2,2)[l]{40}}\put(36,47){\makebox(3.75,2)[r]{CA1}}
\put(32.25,50){\makebox(2,2)[l]{20}}\put(30,48){\makebox(4,2){$\rm V_{DD}$}}
%
% The 74LS153
%
%% The frame and the pins
\thicklines
\put(48,28){\line(0,1){18}\line(1,0){8}\line(0,1){18}}\put(48,46){\line(1,0){8}}
\thinlines
\multiput(47,30)(0,2){8}{\line(1,0){1}}
\multiput(56,30)(0,2){2}{\line(1,0){4}}\multiput(56,38)(0,2){4}{\line(1,0){2}}
\put(52,46){\vector(0,1){2}}
\put(51,26.25){\line(1,0){1}\line(0,1){1.75}\line(1,0){1}}
%% The pin numbers and the labels
\put(46,44){\makebox(1.75,2)[r]{6}}\put(48.25,43){\makebox(4,2)[l]{I0a}}
\put(46,42){\makebox(1.75,2)[r]{10}}\put(48.25,41){\makebox(4,2)[l]{I0b}}
\put(46,40){\makebox(1.75,2)[r]{5}}\put(48.25,39){\makebox(4,2)[l]{I1a}}
\put(46,38){\makebox(1.75,2)[r]{11}}\put(48.25,37){\makebox(4,2)[l]{I1b}}
\put(46,36){\makebox(1.75,2)[r]{4}}\put(48.25,35){\makebox(4,2)[l]{I2a}}
\put(46,34){\makebox(1.75,2)[r]{12}}\put(48.25,33){\makebox(4,2)[l]{I2b}}
\put(46,32){\makebox(1.75,2)[r]{3}}\put(48.25,31){\makebox(4,2)[l]{I3a}}
\put(46,30){\makebox(1.75,2)[r]{13}}\put(48.25,29){\makebox(4,2)[l]{I3b}}
\put(52.25,26.25){\makebox(2,2)[l]{8}}\put(51,28){\makebox(2,2){$\rm V_{SS}$}}
\put(56.25,30){\makebox(2,2)[l]{2}}\put(54,29){\makebox(1.75,2)[r]{S1}}
\put(56.25,32){\makebox(2,2)[l]{14}}\put(54,31){\makebox(1.75,2)[r]{S0}}
\put(56.25,38){\makebox(2,2)[l]{15}}\put(54,37){\makebox(1.75,2)[r]{\overbar{Eb}}}
\put(56.25,40){\makebox(2,2)[l]{1}}\put(54,39){\makebox(1.75,2)[r]{\overbar{Ea}}}
\put(56.25,42){\makebox(2,2)[l]{9}}\put(54,41){\makebox(1.75,2)[r]{Zb}}
\put(56.25,44){\makebox(2,2)[l]{7}}\put(54,43){\makebox(1.75,2)[r]{Za}}
\put(52.25,46){\makebox(2,2)[l]{16}}\put(51,44){\makebox(2,2){$\rm V_{DD}$}}
%
% The 74LS151
%
%% The frame and the pins
\thicklines
\put(48,6){\line(0,1){18}\line(1,0){8}\line(0,1){18}}\put(48,24){\line(1,0){8}}
\thinlines
\multiput(47,8)(0,2){8}{\line(1,0){1}}
\multiput(56,8)(0,2){3}{\line(1,0){1}}\multiput(56,18)(0,2){3}{\line(1,0){2}}
\put(52,24){\vector(0,1){2}}
\put(51,4.25){\line(1,0){1}\line(0,1){1.75}\line(1,0){1}}
%% The pin numbers and the labels
\put(46,22){\makebox(1.75,2)[r]{4}}\put(48.25,21){\makebox(4,2)[l]{I0}}
\put(46,20){\makebox(1.75,2)[r]{3}}\put(48.25,19){\makebox(4,2)[l]{I1}}
\put(46,18){\makebox(1.75,2)[r]{2}}\put(48.25,17){\makebox(4,2)[l]{I2}}
\put(46,16){\makebox(1.75,2)[r]{1}}\put(48.25,15){\makebox(4,2)[l]{I3}}
\put(46,14){\makebox(1.75,2)[r]{15}}\put(48.25,13){\makebox(4,2)[l]{I4}}
\put(46,12){\makebox(1.75,2)[r]{14}}\put(48.25,11){\makebox(4,2)[l]{I5}}
\put(46,10){\makebox(1.75,2)[r]{13}}\put(48.25,9){\makebox(4,2)[l]{I6}}
\put(46,8){\makebox(1.75,2)[r]{12}}\put(48.25,7){\makebox(4,2)[l]{I7}}
\put(52.25,4.25){\makebox(2,2)[l]{8}}\put(51,6){\makebox(2,2){$\rm V_{SS}$}}
\put(56.25,8){\makebox(2,2)[l]{7}}\put(54,7){\makebox(1.75,2)[r]{\overbar{E}}}
\put(56.25,10){\makebox(2,2)[l]{6}}\put(54,9){\makebox(1.75,2)[r]{\overbar{Z}}}
\put(56.25,12){\makebox(2,2)[l]{5}}\put(54,11){\makebox(1.75,2)[r]{Z}}
\put(56.25,18){\makebox(2,2)[l]{11}}\put(54,17){\makebox(1.75,2)[r]{S0}}
\put(56.25,20){\makebox(2,2)[l]{10}}\put(54,19){\makebox(1.75,2)[r]{S1}}
\put(56.25,22){\makebox(2,2)[l]{9}}\put(54,21){\makebox(1.75,2)[r]{S2}}
\put(52.25,24){\makebox(2,2)[l]{16}}\put(51,22){\makebox(2,2){$\rm V_{DD}$}}
%
% The hex inverter 74LS05
%
\put(27,54){\line(1,0){1}\line(0,1){2}\line(1,0){1}}\put(28,54){\makebox(2,2)[l]{7}}
\put(24,57){\makebox(8,4){\parbox{10ex}{\center\bf IC4 74LS05}}}
\put(28,60){\vector(0,1){2}\makebox(2,2)[l]{14}}
%% Port I4
\put(37,54){\line(1,0){1}}\put(38,52){\line(0,1){4}\line(1,1){2}}
\put(40.5,54){\circle{1}}\put(41,54){\line(1,0){1}}\put(40,54){\line(-1,1){2}}
\put(37,54){\makebox(.75,2)[r]{9}}\put(41.25,54){\makebox(.75,2)[l]{8}}
%% Port I3
\put(39,57){\line(1,0){1}}\put(40,55){\line(0,1){4}\line(1,1){2}}
\put(42.5,57){\circle{1}}\put(43,57){\line(1,0){1}}\put(42,57){\line(-1,1){2}}
\put(39,57){\makebox(.75,2)[r]{5}}\put(43.25,57){\makebox(.75,2)[l]{6}}
%% Port I5
\put(37,60){\line(1,0){1}}\put(38,58){\line(0,1){4}\line(1,1){2}}
\put(40.5,60){\circle{1}}\put(41,60){\line(1,0){1}}\put(40,60){\line(-1,1){2}}
\put(37,60){\makebox(.75,2)[r]{11}}\put(41.25,60){\makebox(.75,2)[l]{10}}
%% Port I2
\put(39,63){\line(1,0){1}}\put(40,61){\line(0,1){4}\line(1,1){2}}
\put(42.5,63){\circle{1}}\put(43,63){\line(1,0){1}}\put(42,63){\line(-1,1){2}}
\put(39,63){\makebox(.75,2)[r]{3}}\put(43.25,63){\makebox(.75,2)[l]{4}}
%
% Miscellanous parts
%
%% The serial resistor R1 (33R)
\put(57.2,11){\line(0,1){4}\line(1,0){2}\line(0,1){4}}\put(57.2,15){\line(1,0){2}}
\put(59.2,11){\makebox(4,4){\parbox{5ex}{\center\bf R1 33~$\Omega$}}}
%% The pull-up resistor R2 (4k7)
\put(20,56){\line(0,1){4}\line(1,0){2}\line(0,1){4}}
\put(20,60){\line(1,0){1}\vector(0,1){2}\line(1,0){1}}
\put(21,18){\line(0,1){38}\line(1,0){3}}
\put(21,42){\circle{0}}\put(21,42){\line(1,0){3}}
\put(14,57){\makebox(6,4){\parbox{7.5ex}{\center\bf R2 4.7~k$\Omega$}}}
%% The bypass capacitor C1 (100nF)
\put(12,56){\line(1,0){1}\line(0,1){2.5}\line(1,0){1}}
\multiput(11,58.5)(0,1){2}{\line(1,0){4}}
\put(13,59.5){\vector(0,1){2.5}}
\put(6,57){\makebox(6,4){\parbox{7.5ex}{\center\bf C1 100nF}}}
%
% The connections
%
%% Between the CIA and the PIA
\put(18,16){\line(1,0){6}}               % R/-W
\multiput(18,20)(0,2){10}{\line(1,0){6}} % Clock, Data bus and -RESET
\multiput(18,44)(0,2){2}{\line(1,0){6}}  % RS0 and RS1
%% Between the PIA and the 74LS153
\multiput(40,30)(0,2){8}{\line(1,0){8}}
%% Between the PIA and the 74LS151
\multiput(40,8)(0,2){8}{\line(1,0){8}}
%% The pins CA1 and CA2 of the PIA
\put(40,48){\line(1,0){2}}\put(42,48){\circle{0}}
\put(40,46){\line(1,0){2}\line(0,1){5}}\put(35,51){\line(0,1){12}\line(1,0){7}}
\multiput(35,54)(0,3){3}{\circle{0}}
\multiput(35,54)(0,6){2}{\line(1,0){3}}
\multiput(35,57)(0,6){2}{\line(1,0){5}}
\put(42,54){\line(1,0){1}\line(0,-1){10}}\put(43,44){\circle{0}}
\put(44,57){\line(0,-1){15}}\put(44,42){\circle{0}}
\put(42,60){\line(1,0){3}\line(0,-1){22}}\put(45,38){\circle{0}}
\put(44,63){\line(1,0){2}\line(0,-1){27}}\put(46,36){\circle{0}}
%% The 74LS153 and the 74LS151
\put(58,43.2){\framebox(3,1.6){\small B15}}
\put(58,41.2){\framebox(3,1.6){\small B14}}
\put(57,36){\line(1,0){1}\line(0,1){4}\line(1,0){1}}\put(58,38){\circle{0}}
\put(58,22){\line(0,1){8}}\put(58,30){\circle{0}}
\put(60,31.2){\framebox(3,1.6){\small A14}}
\put(58,20){\line(1,0){1}\line(0,1){12}}\put(59,32){\circle{0}}
\put(60,29.2){\framebox(3,1.6){\small A15}}
\put(58,17.2){\framebox(4,1.6){\small MUX}}
\put(57,10){\line(1,0){1.1}\line(0,1){1}}\put(58.1,16){\line(0,-1){1}\line(1,0){.9}}
\put(59,15.2){\framebox(4,1.6){\small MA8}}
\put(57,8){\line(1,0){1}}\put(57,6){\line(1,0){1}\line(0,1){2}\line(1,0){1}}
\put(16,7){\framebox(4,2){\small\overbar{I/O2}}}
\put(17,9.2){\framebox(3,1.6){\small A7}}

\end{picture}
\end{center}
\caption{The schematics diagram of the PIA expansion. See text.}
\label{PIAschematics}
\end{figure}

\begin{figure}
\setlength{\unitlength}{1.5ex}
\begin{center}
\begin{picture}(20,16)(-5,0)
% Caption
\put(-5,16){\makebox(20,2){\bf U14 74LS257A}}
% The Dual-In-Line housing
\thicklines
\put(1,0){\line(1,0){8}}\put(1,0){\line(0,1){16}}
\put(9,0){\line(0,1){16}}\put(1,16){\line(1,0){8}}
\put(5,16){\oval(2,2)[b]}\put(1.5,15.5){\circle{0}}
% The pins
\thinlines
\multiput(0,1)(0,2){8}{\line(1,0){1}}
\multiput(9,1)(0,2){8}{\line(1,0){1}}
% The pin numbers
\put(2,14){\makebox(2,2)[l]{1}}
\put(6,14){\makebox(2,2)[r]{16}}
\put(2,12){\makebox(2,2)[l]{2}}
\put(6,12){\makebox(2,2)[r]{15}}
\put(2,10){\makebox(2,2)[l]{3}}
\put(6,10){\makebox(2,2)[r]{14}}
\put(2,8){\makebox(2,2)[l]{4}}
\put(6,8){\makebox(2,2)[r]{13}}
\put(2,6){\makebox(2,2)[l]{5}}
\put(6,6){\makebox(2,2)[r]{12}}
\put(2,4){\makebox(2,2)[l]{6}}
\put(6,4){\makebox(2,2)[r]{11}}
\put(2,2){\makebox(2,2)[l]{7}}
\put(6,2){\makebox(2,2)[r]{10}}
\put(2,0){\makebox(2,2)[l]{8}}
\put(6,0){\makebox(2,2)[r]{9}}
% The descriptions
\put(-5,14){\makebox(5,2)[r]{MUX}}
\put(10,14){\makebox(5,2)[l]{$\rm V_{DD}$}}
\put(-5,12){\makebox(5,2)[r]{TA15}}
\put(10,12){\makebox(5,2)[l]{\overbar{AEC}}}
\put(-5,10){\makebox(5,2)[r]{A7}}
\put(10,10){\makebox(5,2)[l]{TA12}}
\put(-5,8){\makebox(5,2)[r]{VMA7}}
\put(10,8){\makebox(5,2)[l]{A4}}
\put(-5,6){\makebox(5,2)[r]{TA14}}
\put(10,6){\makebox(5,2)[l]{VMA4}}
\put(-5,4){\makebox(5,2)[r]{A6}}
\put(10,4){\makebox(5,2)[l]{TA13}}
\put(-5,2){\makebox(5,2)[r]{VMA6}}
\put(10,2){\makebox(5,2)[l]{A5}}
\put(-5,0){\makebox(5,2)[r]{$\rm V_{SS}$}}
\put(10,0){\makebox(5,2)[l]{VMA5}}
\end{picture}
\end{center}
\caption{Pin-out for the multiplexer chip U14}
\label{U14_pins}
\end{figure}

\begin{figure}[hbt]
\setlength{\unitlength}{1.5ex}
\begin{center}
\begin{picture}(52,40)(-3,0)
% Captions
\put(-5,40){\makebox(26,2){\bf MOS~6526~CIA}}
\put(25,40){\makebox(26,2){\bf MC~6821~PIA}}
% The Dual-In-Line housings
\thicklines
\multiput(1,0)(30,0){2}{\line(0,1){40}\line(1,0){14}\line(0,1){40}}
\multiput(1,40)(30,0){2}{\line(1,0){14}}
\multiput(8,40)(30,0){2}{\oval(2,2)[b]}
\multiput(1.5,39.5)(30,0){2}{\circle{0}}
% The pins
\thinlines
\multiput(0,1)(0,2){20}{\line(1,0){1}}
\multiput(15,1)(0,2){20}{\line(1,0){1}}
\multiput(30,1)(0,2){20}{\line(1,0){1}}
\multiput(45,1)(0,2){20}{\line(1,0){1}}
% The pin numbers
\multiput(2,38)(30,0){2}{\makebox(2,2)[l]{1}}
\multiput(2,36)(30,0){2}{\makebox(2,2)[l]{2}}
\multiput(2,34)(30,0){2}{\makebox(2,2)[l]{3}}
\multiput(2,32)(30,0){2}{\makebox(2,2)[l]{4}}
\multiput(2,30)(30,0){2}{\makebox(2,2)[l]{5}}
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\multiput(2,26)(30,0){2}{\makebox(2,2)[l]{7}}
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\multiput(2,20)(30,0){2}{\makebox(2,2)[l]{10}}
\multiput(2,18)(30,0){2}{\makebox(2,2)[l]{11}}
\multiput(2,16)(30,0){2}{\makebox(2,2)[l]{12}}
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\multiput(2,0)(30,0){2}{\makebox(2,2)[l]{20}}
\multiput(12,0)(30,0){2}{\makebox(2,2)[r]{21}}
\multiput(12,2)(30,0){2}{\makebox(2,2)[r]{22}}
\multiput(12,4)(30,0){2}{\makebox(2,2)[r]{23}}
\multiput(12,6)(30,0){2}{\makebox(2,2)[r]{24}}
\multiput(12,8)(30,0){2}{\makebox(2,2)[r]{25}}
\multiput(12,10)(30,0){2}{\makebox(2,2)[r]{26}}
\multiput(12,12)(30,0){2}{\makebox(2,2)[r]{27}}
\multiput(12,14)(30,0){2}{\makebox(2,2)[r]{28}}
\multiput(12,16)(30,0){2}{\makebox(2,2)[r]{29}}
\multiput(12,18)(30,0){2}{\makebox(2,2)[r]{30}}
\multiput(12,20)(30,0){2}{\makebox(2,2)[r]{31}}
\multiput(12,22)(30,0){2}{\makebox(2,2)[r]{32}}
\multiput(12,24)(30,0){2}{\makebox(2,2)[r]{33}}
\multiput(12,26)(30,0){2}{\makebox(2,2)[r]{34}}
\multiput(12,28)(30,0){2}{\makebox(2,2)[r]{35}}
\multiput(12,30)(30,0){2}{\makebox(2,2)[r]{36}}
\multiput(12,32)(30,0){2}{\makebox(2,2)[r]{37}}
\multiput(12,34)(30,0){2}{\makebox(2,2)[r]{38}}
\multiput(12,36)(30,0){2}{\makebox(2,2)[r]{39}}
\multiput(12,38)(30,0){2}{\makebox(2,2)[r]{40}}
% The descriptions
\multiput(-5,38)(30,0){2}{\makebox(5,2)[r]{$\rm V_{SS}$}}
\multiput(-5,36)(30,0){2}{\makebox(5,2)[r]{PA0}}
\multiput(-5,34)(30,0){2}{\makebox(5,2)[r]{PA1}}
\multiput(-5,32)(30,0){2}{\makebox(5,2)[r]{PA2}}
\multiput(-5,30)(30,0){2}{\makebox(5,2)[r]{PA3}}
\multiput(-5,28)(30,0){2}{\makebox(5,2)[r]{PA4}}
\multiput(-5,26)(30,0){2}{\makebox(5,2)[r]{PA5}}
\multiput(-5,24)(30,0){2}{\makebox(5,2)[r]{PA6}}
\multiput(-5,22)(30,0){2}{\makebox(5,2)[r]{PA7}}
\multiput(-5,20)(30,0){2}{\makebox(5,2)[r]{PB0}}
\multiput(-5,18)(30,0){2}{\makebox(5,2)[r]{PB1}}
\multiput(-5,16)(30,0){2}{\makebox(5,2)[r]{PB2}}
\multiput(-5,14)(30,0){2}{\makebox(5,2)[r]{PB3}}
\multiput(-5,12)(30,0){2}{\makebox(5,2)[r]{PB4}}
\multiput(-5,10)(30,0){2}{\makebox(5,2)[r]{PB5}}
\multiput(-5,8)(30,0){2}{\makebox(5,2)[r]{PB6}}
\multiput(-5,6)(30,0){2}{\makebox(5,2)[r]{PB7}}
\put(-5,4){\makebox(5,2)[r]{\overbar{PC}}}
\put(-5,2){\makebox(5,2)[r]{TOD}}
\put(25,4){\makebox(5,2)[r]{CB1}}
\put(25,2){\makebox(5,2)[r]{CB2}}
\multiput(-5,0)(30,0){2}{\makebox(5,2)[r]{$\rm V_{DD}$}}
\put(16,0){\makebox(5,2)[l]{\overbar{IRQ}}}
\put(16,2){\makebox(5,2)[l]{R/\overbar{W}}}
\put(16,4){\makebox(5,2)[l]{\overbar{CS}}}
\put(16,6){\makebox(5,2)[l]{\overbar{FLAG}}}
\put(16,8){\makebox(5,2)[l]{$\rm \Phi_2$}}
\put(46,0){\makebox(5,2)[l]{R/\overbar{W}}}
\put(46,2){\makebox(5,2)[l]{CS0}}
\put(46,4){\makebox(5,2)[l]{\overbar{CS2}}}
\put(46,6){\makebox(5,2)[l]{CS1}}
\put(46,8){\makebox(5,2)[l]{E}}
\multiput(16,10)(30,0){2}{\makebox(5,2)[l]{D7}}
\multiput(16,12)(30,0){2}{\makebox(5,2)[l]{D6}}
\multiput(16,14)(30,0){2}{\makebox(5,2)[l]{D5}}
\multiput(16,16)(30,0){2}{\makebox(5,2)[l]{D4}}
\multiput(16,18)(30,0){2}{\makebox(5,2)[l]{D3}}
\multiput(16,20)(30,0){2}{\makebox(5,2)[l]{D2}}
\multiput(16,22)(30,0){2}{\makebox(5,2)[l]{D1}}
\multiput(16,24)(30,0){2}{\makebox(5,2)[l]{D0}}
\multiput(16,26)(30,0){2}{\makebox(5,2)[l]{\overbar{RESET}}}
\put(16,28){\makebox(5,2)[l]{RS3}}
\put(16,30){\makebox(5,2)[l]{RS2}}
\put(16,32){\makebox(5,2)[l]{RS1}}
\put(16,34){\makebox(5,2)[l]{RS0}}
\put(16,36){\makebox(5,2)[l]{SP}}
\put(16,38){\makebox(5,2)[l]{CNT}}
\put(46,28){\makebox(5,2)[l]{RS1}}
\put(46,30){\makebox(5,2)[l]{RS0}}
\put(46,32){\makebox(5,2)[l]{\overbar{IRQB}}}
\put(46,34){\makebox(5,2)[l]{\overbar{IRQA}}}
\put(46,36){\makebox(5,2)[l]{CA2}}
\put(46,38){\makebox(5,2)[l]{CA1}}
\end{picture}
\caption{The CIA and the PIA}
\label{CIAPIA}
\end{center}
\end{figure}

\begin{table}
\begin{center}
\begin{tabular}{|l|l|}
\hline
\multicolumn{2}{|c|}{\bf Electronic Components} \\ \hline
\multicolumn{1}{|c}{Symbol} & \multicolumn{1}{|c|}{Description} \\
\hline
IC1      & MC 6821 \\
IC2      & 74LS153 (or 74LS253) \\
IC3      & 74LS151 (or 74LS251) \\
IC4      & 74LS05 \\
U38--U53 & 80256 or compatible \\
C1       & 100 nF polyester capacitor \\
R1       & 33 $\Omega$ resistor \\
R2       & 4.7 k$\Omega$ resistor \\
\hline
\hline
\multicolumn{2}{|c|}{\bf Other Parts} \\ \hline
\multicolumn{1}{|c}{Quantity} & \multicolumn{1}{|c|}{Quality} \\
\hline 
2 pcs     & \parbox{2.3in}{\smallskip
            20-pin through-put connectors
            (piggyback socket halves)
            \smallskip} \\
1 pc      & \parbox{2.3in}{\smallskip
            40-pin socket (if U1 is not socketed)
            \smallskip} \\
1 pc      & 16-pin socket \\
plenty of & connection wire \\
\hline
\end{tabular}
\end{center}
\caption{Parts list for the PIA expansion}
\end{table}

\subsubsection{Removing the old memory chips}

First you have to remove the memory chips U38 through U53. If you look
at the mother board from the front of the computer as if you were
typing, the chips are on the front left in two rows of eight chips.
They are of type 4164 (or 3164 or 6665 or 6664 or 8064 or\ldots). You
could install the new chips into sockets, but I thought that it is a
waste of money.

If these memory chips are already on sockets, the most of the work is
done for you. It helps a lot, if you remove the bypass capacitors
before removing the chips. Removing the components is easiest with a
desoldering pump. It becomes even easier, when you first solder the
pins with fresh solder, so that the hartz from it makes the removal of
old solder easier.

Using much power is questionable, as the copper folio comes off the
board in a surprisingly easy way. As usual, I used a screwdriver like
a crowbar, and the through-coppering got lost from several places.
This was not crucial, as those pins were connected only to the down
side of the board. However, three or four routes broke on the top side
also. This made it far more difficult (and slower) to solder the new
chips in, but I succeeded on the first try.

After you have removed the 4164s, you can solder the 16-pin sockets
(or the 41256 memory chips) into their places. You can solder the
capacitors back as well, if you removed them.

\subsubsection{Adding the new address line}

You must connect the pin~1 of each memory chip (or socket). It is the
extra address line (MA8) to the switcher. The best way is to solder a
Wire-Wrap wire to each contact under the mother board, but any thin
and pliable uni-strand wire should do. The wire does not affect in any
way the computer's operation with 64~kb chips.

After the pins have been connected together, they must be temporarily
connected to +5~V, which is in the pin~8 of the memory chips. Comparing
to TTL chips, the operating voltages are `reversed' in dynamic memories.

Now the new 256~kb memory chips can be installed to the sockets
(preferably right-side forward), and you can try switching the power
on. You do not have to connect anything except the power cable and the
cable to the TV set or monitor. Ensure that the ``40/80 display'' key
is up, and that the monitor is set to display the 40 column screen,
too. It is a good idea to turn on the monitor first and let it warm
up, so that it will show the picture from the very beginning.

If the screen shows up normally, you may not (yet) have made any
mistakes. If it does not show up at all, you have to find possible
cut-outs and shorts. Multi-colored `{\tt\verb|@|}'s show up usually
because of too small bypass capacitors. Another cause is that the
pin~1 is not connected to +5~V. In this case the screen may come up
normally, but a little disturbance in the operating voltage locks the
computer up. Now the computer should operate exactly like an
unexpanded C128, so any previously working program should work with it.

\subsubsection{Prepare for the final step}

Next you remove U14 (74LS257, to the right of the memory chips) and U1
(MOS~6526, near the keyboard connector). Either or both of these chips
may already be on sockets, and you must remove the rest. Reinsert the
chips and check if the machine boots up.

If the computer does not work on first try, remember to disconnect any
cables from it before trying to fix the problem. The soldering iron
may occasionally give little electric pulses to the computer, and this
might burn some expensive chips, especially if the computer is hooked
to a wall outlet or a television set.

When you have completed the preparations, you can start building the
control logic. You could build the whole expansion by piggy-backing
chips, that is, by soldering new chips on the top of old ones, bending
some feet to the side, and connecting messy wires all over your
computer. However, the best way is to put most of the chips on a
daughter board. I used only a small daughter board, and piggy-backed
five or six chips, but you can be wiser and put all new chips on the
daughter board.

My daughter board interfaces the heart of the expansion, MC~6821~PIA,
to the bus of the computer through the pins of U1, the MOS~6526~CIA
near the keyboard connector. The CIA is raised on the board, and its
pins are lenghtened with two through-put socket halves, so that they
can reach the socket on the mother board. I built the daughter board
on an uncoppered prototype board, a plastic board with holes punched
in it at a 1/10 inch grid.

The room reserved for the mother board in the C128 and C128D is very
shallow, about one third of the height in the C64. In addition to
that, the front edge of the mother board must be even shallower, as
the metal shield has an angle in it. Due to this, you cannot use any
sockets in the CIA daughter board, and you have to choose the chip
layout very carefully. My daughter board has the PIA chip on the left
side of the CIA. To leave room for the MMU expansion, I could put only
two chips (IC2 and IC3) horizontally next to the notched end of the
PIA (IC1) and CIA (U1). I placed the inverter (IC4) with the 100~nF
bypass capacitor near the other end of the PIA chip.

A far better way is to interface the daughter board to the socket of
U7 (MOS~8722~MMU). There are not so terrible space limitations, the
RF shield is higher near the rear edge of the machine than on the
front edge. In addition to that, the keyboard cable of the flat C128
is not so likely to damage that daughter board than the CIA board,
which would be next to the keyboard connector. The MMU daughter board
would allow you to make an easily removable expansion, as no chips
would be piggy-backed. You could even make an option for installing a
second MOS~6581\footnote{8580 for the 9 volt version}~SID (Sound
Interface Device) on the board to get stereo sound. However, this
board should be etched, as the PIA and MMU pin layouts differ very
much from each other. See Figure \ref{MMUpins} for pinouts for the
MMU. Pinouts for the PIA and CIA are presented in Figure \ref{CIAPIA}.

Building the CIA daughter board was a real pain. I had to solder the
CIA directly to the piggy-back socket pins, and I even bent the CIA
pin ends aside, so that I could make it about 1~mm shallower. I put
the CIA pins and the through-put socket halves to the same holes and
started soldering. To keep the socket halves parallel, I put one half
against the outside of the CIA pins, and the other half against the
inside. It was very easy to solder the half whose contacts were
outside the pins, but the other half was a real pain. It could be done
by heating a CIA pin, inserting some solder from the side, and hoping
that it connects the piggy-back socket pin. I had to solder those pins
four or five times.

After raising the CIA on the daughter board, it is a very good idea to
insert the board to the socket and check if the machine boots up. If
some of the right side pins (21--40) are loose, the machine can jump
to ML monitor due to an unexpected interrupt, or it can misread the
keyboard. In the C64 mode, it will probably jam.

The next step is to add the PIA on the board. The contacts from the
CIA except the operating voltages may be difficult to route. I solved
the problem by putting the wires through the very small holes that
were left between the biggy-back socket halves and the down surface of
the daughter board. It was very painful, but the design is very
compact. After soldering all CIA contacts to the PIA, I wired the
inverter and the rest of the chips. To increase reliability, I used
thin multi-strand wire, as uni-strand wire gets easily loose when you
push it.

Since I had finished the daughter board, I bent up the pins 2 and 5 of
the U14 multiplexer chip, and connected its pins 1--3 and 5 to the
daughter board with wires. First I inserted the wires for A14 and A15
directly to the chip socket, but as it turned out to be unreliable, I
located a through-put place for each line, and soldered the wires
there instead.

When you have wired the multiplexer U14, remove the jumper wire
between MA8 and +5~V and connect that address line to the daughter
board. Then connect the PIA's \overbar{CS} line to \overbar{I/O2},
which is in U3's pin~7 (or one of the through-put places along the
trace's path to the cartridge port), and insert the daughter board to
the socket. Switch the power on and pray that your dear computer
works.

If you get only crap consisting of {\tt\verb|@|}'s or some randomly
changing graphics on the 40 column screen, check that all CIA pins
have a good contact to the piggy-back socket, and that the wires from
U14 and its socket are firmly connected. If it doesn't help, you have
to check all daughter board connections with the continuity
tester. Don't panic, you can ensure that the computer works by
connecting the MA8 line back to +5~V, by bending the U14 lines back
down, and by inserting a spare CIA chip to the CIA socket.

\subsubsection{Testing}

After you have installed the boards to your machine, it is time to
test the connections. You can connect LED, keyboard and probably disk
drive in addition to the power cable and the TV cable, but do not
fasten the mounting screws yet. If the 40 column screen shows up and
if the machine seems to operate, input the following test program:

\begin{quote}
\begin{verbatim}
10 PB=57282
20 POKE PB,255:POKE PB+1,4:POKE PB,255
30 PRINT"PRESS A KEY AFTER THIS HAS DISAPPEARED":
   FOR I=0 TO 3000:NEXT
40 POKE PB,14:WAIT 198,15:GET A$:POKE PB,255
\end{verbatim}
\end{quote}

On the line {\tt 10} a variable {\tt PB} is set up. It is the address
of the peripheral and data direction registers for the 6821 port~B,
and the block selection register of the segments {\tt 2} and {\tt 3}
and the VIC-IIe.

The line {\tt 20} contains initialization of PIA: the lines PB0--PB7
are set outputs, the data direction register is switched to data
register with `{\tt POKE~PB+1,4}', and the PB lines are set high.

On the line {\tt 40} VIC-IIe is given block~{\tt 0} ({\tt\$00000}--%
{\tt\$0FFFF}) of the default bank ({\tt 0}), and then the program
waits for a keypress and restores the block~{\tt F}
({\tt\$30000}--{\tt\$3FFFF}).

If this test program works as expected, the screen will be filled with
`{\tt\verb|@|}'s and other random characters.

At this point, you may want to switch to the C64 mode and to run the
{\tt TEST} program, which is among the distribution files.%
\footnote{See Section~\ref{TEST}.} Also, you can try the
{\tt PIAGLOBE.128} program to test almost all of the 512~kB or 1024~kB
memory.

The {\tt PIAGLOBE.128} program is based on Georg Schwarz's globe
spinner {\tt GLOBE.64} that uses two graphics screens. He has made a
slightly faster version for the C128, utilizing the 2 MHz mode in the
screen border. But compared to it, {\tt PIAGLOBE.128} is from other
planet. Depending on the amount of memory available, it calculates 112
or 56 pictures of the globe and then uses them in a continuous
animation. One revolution will last approximately 2.23 seconds on PAL
systems and 1.87 seconds on NTSC. As the calculation phase lasts more
than a minute, the program changes the screen color between each
picture.

On NTSC systems, the edge of the globe might not display correctly.
The edge is rounded with 24 sprites, which are moved around by a
raster interrupt routine, starting from {\tt\$4801}. I did not bother
to think about the timings, since I had enough troubles with
relocating the program and the tables, and in trying to get all that
graphics data to fit in the memory. In the distant future I might make
a better looking version of the globe spinner, who knows. There is
over 80 kilobytes of unused memory when running the program on a
C1028.

\subsection{Expanding to 256 or 1024 kilobytes}

This MMU expansion is far easier to understand than the PIA expansion,
and maybe faster to build, too. You have to solder the new MMU and a
couple of logic chips on top of some chips laying on the mother board,
or to install them on a daughter board. I chose the piggy-backing
method.

\begin{figure}
\setlength{\unitlength}{1.1ex}
\begin{center}
\begin{picture}(72,96)(1,0)
%
% Captions
%
\put(6,55){\makebox(8,6){\parbox{8.8ex}{\center\bf U7 M8722 MMU}}}
\put(36,55){\makebox(8,6){\parbox{8.8ex}{\center\bf IC5 M8722 MMU}}}
\put(50,84){\makebox(8,4){\parbox{8.8ex}{\center\bf IC9 74F32}}}
\put(64,84){\makebox(8,4){\parbox{8.8ex}{\center\bf U9 74F32}}}
\put(6,11){\makebox(6,4){\parbox{6.6ex}{\center\bf U20 4066}}}
\put(20,11){\makebox(6,4){\parbox{6.6ex}{\center\bf IC8 4066}}}
\put(30,12){\makebox(8,4){\parbox{8.8ex}{\center\bf IC7 74F00}}}
\put(52,11){\makebox(6,4){\parbox{6.6ex}{\center\bf IC6 '138}}}
\put(64,11){\makebox(6,4){\parbox{6.6ex}{\center\bf U3 '138}}}
%
% The U7 (MOS 8722 MMU)
%
%% The frame and the pins
\thicklines
\put(4,24){\line(0,1){68}\line(1,0){16}\line(0,1){68}}\put(4,92){\line(1,0){16}}
\thinlines
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\multiput(20,26)(0,2){33}{\line(1,0){1}}
\put(12,92){\vector(0,1){2}}
\put(11,22){\line(1,0){1}\line(0,1){2}\line(1,0){1}}
%% The pin numbers and the labels
\put(2,90){\makebox(1.75,2)[r]{\small 3}}\put(4.25,89){\makebox(4,2)[l]{TA15}}
\put(2,88){\makebox(1.75,2)[r]{\small 4}}\put(4.25,87){\makebox(4,2)[l]{TA14}}
\put(2,86){\makebox(1.75,2)[r]{\small 5}}\put(4.25,85){\makebox(4,2)[l]{TA13}}
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\put(2,76){\makebox(1.75,2)[r]{\small 10}}\put(4.25,75){\makebox(4,2)[l]{TA8}}
\put(2,74){\makebox(1.75,2)[r]{\small 11}}\put(4.25,73){\makebox(4,2)[l]{\overbar{CAS1}}}
\put(2,72){\makebox(1.75,2)[r]{\small 12}}\put(4.25,71){\makebox(4,2)[l]{\overbar{CAS0}}}
\put(2,70){\makebox(1.75,2)[r]{\small 13}}\put(4.25,69){\makebox(4,2)[l]{MS2}}
\put(2,68){\makebox(1.75,2)[r]{\small 14}}\put(4.25,67){\makebox(4,2)[l]{MS1}}
\put(2,66){\makebox(1.75,2)[r]{\small 15}}\put(4.25,65){\makebox(4,2)[l]{MS0}}
\put(12.25,22){\makebox(2,2)[l]{\small 34}}\put(10,24){\makebox(4,2){$\rm V_{SS}$}}
\put(20.25,26){\makebox(2,2)[l]{\small 48}}\put(16,25){\makebox(3.75,2)[r]{40/\overbar{80}}}
\put(20.25,28){\makebox(2,2)[l]{\small 47}}\put(16,27){\makebox(3.75,2)[r]{MS3}}
\put(20.25,30){\makebox(2,2)[l]{\small 46}}\put(16,29){\makebox(3.75,2)[r]{\overbar{EXROM}}}
\put(20.25,32){\makebox(2,2)[l]{\small 45}}\put(16,31){\makebox(3.75,2)[r]{\overbar{GAME}}}
\put(20.25,34){\makebox(2,2)[l]{\small 44}}\put(16,33){\makebox(3.75,2)[r]{\overbar{FSDIR}}}
\put(20.25,36){\makebox(2,2)[l]{\small 43}}\put(16,35){\makebox(3.75,2)[r]{\overbar{Z80EN}}}
\put(20.25,38){\makebox(2,2)[l]{\small 42}}\put(16,37){\makebox(3.75,2)[r]{D7}}
\put(20.25,40){\makebox(2,2)[l]{\small 41}}\put(16,39){\makebox(3.75,2)[r]{D6}}
\put(20.25,42){\makebox(2,2)[l]{\small 40}}\put(16,41){\makebox(3.75,2)[r]{D5}}
\put(20.25,44){\makebox(2,2)[l]{\small 39}}\put(16,43){\makebox(3.75,2)[r]{D4}}
\put(20.25,46){\makebox(2,2)[l]{\small 38}}\put(16,45){\makebox(3.75,2)[r]{D3}}
\put(20.25,48){\makebox(2,2)[l]{\small 37}}\put(16,47){\makebox(3.75,2)[r]{D2}}
\put(20.25,50){\makebox(2,2)[l]{\small 36}}\put(16,49){\makebox(3.75,2)[r]{D1}}
\put(20.25,52){\makebox(2,2)[l]{\small 35}}\put(16,51){\makebox(3.75,2)[r]{D0}}
\put(20.25,54){\makebox(2,2)[l]{\small 33}}\put(16,53){\makebox(3.75,2)[r]{$\rm\Phi_{IN}$}}
\put(20.25,56){\makebox(2,2)[l]{\small 32}}\put(16,55){\makebox(3.75,2)[r]{R/\overbar{W}}}
\put(20.25,58){\makebox(2,2)[l]{\small 31}}\put(16,57){\makebox(3.75,2)[r]{A15}}
\put(20.25,60){\makebox(2,2)[l]{\small 30}}\put(16,59){\makebox(3.75,2)[r]{A14}}
\put(20.25,62){\makebox(2,2)[l]{\small 29}}\put(16,61){\makebox(3.75,2)[r]{A13}}
\put(20.25,64){\makebox(2,2)[l]{\small 28}}\put(16,63){\makebox(3.75,2)[r]{A12}}
\put(20.25,66){\makebox(2,2)[l]{\small 27}}\put(16,65){\makebox(3.75,2)[r]{A11}}
\put(20.25,68){\makebox(2,2)[l]{\small 26}}\put(16,67){\makebox(3.75,2)[r]{A10}}
\put(20.25,70){\makebox(2,2)[l]{\small 25}}\put(16,69){\makebox(3.75,2)[r]{A9}}
\put(20.25,72){\makebox(2,2)[l]{\small 24}}\put(16,71){\makebox(3.75,2)[r]{A8}}
\put(20.25,74){\makebox(2,2)[l]{\small 23}}\put(16,73){\makebox(3.75,2)[r]{A7/A6}}
\put(20.25,76){\makebox(2,2)[l]{\small 22}}\put(16,75){\makebox(3.75,2)[r]{A5/A4}}
\put(20.25,78){\makebox(2,2)[l]{\small 21}}\put(16,77){\makebox(3.75,2)[r]{A3}}
\put(20.25,80){\makebox(2,2)[l]{\small 20}}\put(16,79){\makebox(3.75,2)[r]{A2}}
\put(20.25,82){\makebox(2,2)[l]{\small 19}}\put(16,81){\makebox(3.75,2)[r]{A1}}
\put(20.25,84){\makebox(2,2)[l]{\small 18}}\put(16,83){\makebox(3.75,2)[r]{A0}}
\put(20.25,86){\makebox(2,2)[l]{\small 17}}\put(16,85){\makebox(3.75,2)[r]{MUX}}
\put(20.25,88){\makebox(2,2)[l]{\small 16}}\put(16,87){\makebox(3.75,2)[r]{AEC}}
\put(20.25,90){\makebox(2,2)[l]{\small 2}}\put(16,89){\makebox(3.75,2)[r]{\overbar{RESET}}}
\put(12.25,92){\makebox(2,2)[l]{\small 1}}\put(10,94){\makebox(4,2){$\rm V_{DD}$}}
%
% The IC5 (MOS 8722 MMU)
%
%% The frame and the pins
\thicklines
\put(30,24){\line(0,1){68}\line(1,0){16}\line(0,1){68}}\put(30,92){\line(1,0){16}}
\thinlines
\multiput(29,26)(0,2){33}{\line(1,0){1}}
\multiput(46,66)(0,2){13}{\line(1,0){1}}
\put(38,92){\vector(0,1){2}}
\put(37,22){\line(1,0){1}\line(0,1){2}\line(1,0){1}}
%% The pin numbers and the labels
\put(46.25,90){\makebox(2,2)[l]{\small 3}}\put(42,89){\makebox(3.75,2)[r]{TA15}}
\put(46.25,88){\makebox(2,2)[l]{\small 4}}\put(42,87){\makebox(3.75,2)[r]{TA14}}
\put(46.25,86){\makebox(2,2)[l]{\small 5}}\put(42,85){\makebox(3.75,2)[r]{TA13}}
\put(46.25,84){\makebox(2,2)[l]{\small 6}}\put(42,83){\makebox(3.75,2)[r]{TA12}}
\put(46.25,82){\makebox(2,2)[l]{\small 7}}\put(42,81){\makebox(3.75,2)[r]{TA11}}
\put(46.25,80){\makebox(2,2)[l]{\small 8}}\put(42,79){\makebox(3.75,2)[r]{TA10}}
\put(46.25,78){\makebox(2,2)[l]{\small 9}}\put(42,77){\makebox(3.75,2)[r]{TA9}}
\put(46.25,76){\makebox(2,2)[l]{\small 10}}\put(42,75){\makebox(3.75,2)[r]{TA8}}
\put(46.25,74){\makebox(2,2)[l]{\small 11}}\put(42,73){\makebox(3.75,2)[r]{\overbar{CAS1}}}
\put(46.25,72){\makebox(2,2)[l]{\small 12}}\put(42,71){\makebox(3.75,2)[r]{\overbar{CAS0}}}
\put(46.25,70){\makebox(2,2)[l]{\small 13}}\put(42,69){\makebox(3.75,2)[r]{MS2}}
\put(46.25,68){\makebox(2,2)[l]{\small 14}}\put(42,67){\makebox(3.75,2)[r]{MS1}}
\put(46.25,66){\makebox(2,2)[l]{\small 15}}\put(42,65){\makebox(3.75,2)[r]{MS0}}
\put(38.25,22){\makebox(2,2)[l]{\small 34}}\put(36,24){\makebox(4,2){$\rm V_{SS}$}}
\put(28,26){\makebox(1.75,2)[r]{\small 48}}\put(30.25,25){\makebox(4,2)[l]{40/\overbar{80}}}
\put(28,28){\makebox(1.75,2)[r]{\small 47}}\put(30.25,27){\makebox(4,2)[l]{MS3}}
\put(28,30){\makebox(1.75,2)[r]{\small 46}}\put(30.25,29){\makebox(4,2)[l]{\overbar{EXROM}}}
\put(28,32){\makebox(1.75,2)[r]{\small 45}}\put(30.25,31){\makebox(4,2)[l]{\overbar{GAME}}}
\put(28,34){\makebox(1.75,2)[r]{\small 44}}\put(30.25,33){\makebox(4,2)[l]{\overbar{FSDIR}}}
\put(28,36){\makebox(1.75,2)[r]{\small 43}}\put(30.25,35){\makebox(4,2)[l]{\overbar{Z80EN}}}
\put(28,38){\makebox(1.75,2)[r]{\small 42}}\put(30.25,37){\makebox(4,2)[l]{D7}}
\put(28,40){\makebox(1.75,2)[r]{\small 41}}\put(30.25,39){\makebox(4,2)[l]{D6}}
\put(28,42){\makebox(1.75,2)[r]{\small 40}}\put(30.25,41){\makebox(4,2)[l]{D5}}
\put(28,44){\makebox(1.75,2)[r]{\small 39}}\put(30.25,43){\makebox(4,2)[l]{D4}}
\put(28,46){\makebox(1.75,2)[r]{\small 38}}\put(30.25,45){\makebox(4,2)[l]{D3}}
\put(28,48){\makebox(1.75,2)[r]{\small 37}}\put(30.25,47){\makebox(4,2)[l]{D2}}
\put(28,50){\makebox(1.75,2)[r]{\small 36}}\put(30.25,49){\makebox(4,2)[l]{D1}}
\put(28,52){\makebox(1.75,2)[r]{\small 35}}\put(30.25,51){\makebox(4,2)[l]{D0}}
\put(28,54){\makebox(1.75,2)[r]{\small 33}}\put(30.25,53){\makebox(4,2)[l]{$\rm\Phi_{IN}$}}
\put(28,56){\makebox(1.75,2)[r]{\small 32}}\put(30.25,55){\makebox(4,2)[l]{R/\overbar{W}}}
\put(28,58){\makebox(1.75,2)[r]{\small 31}}\put(30.25,57){\makebox(4,2)[l]{A15}}
\put(28,60){\makebox(1.75,2)[r]{\small 30}}\put(30.25,59){\makebox(4,2)[l]{A14}}
\put(28,62){\makebox(1.75,2)[r]{\small 29}}\put(30.25,61){\makebox(4,2)[l]{A13}}
\put(28,64){\makebox(1.75,2)[r]{\small 28}}\put(30.25,63){\makebox(4,2)[l]{A12}}
\put(28,66){\makebox(1.75,2)[r]{\small 27}}\put(30.25,65){\makebox(4,2)[l]{A11}}
\put(28,68){\makebox(1.75,2)[r]{\small 26}}\put(30.25,67){\makebox(4,2)[l]{A10}}
\put(28,70){\makebox(1.75,2)[r]{\small 25}}\put(30.25,69){\makebox(4,2)[l]{A9}}
\put(28,72){\makebox(1.75,2)[r]{\small 24}}\put(30.25,71){\makebox(4,2)[l]{A8}}
\put(28,74){\makebox(1.75,2)[r]{\small 23}}\put(30.25,73){\makebox(4,2)[l]{A7/A6}}
\put(28,76){\makebox(1.75,2)[r]{\small 22}}\put(30.25,75){\makebox(4,2)[l]{A5/A4}}
\put(28,78){\makebox(1.75,2)[r]{\small 21}}\put(30.25,77){\makebox(4,2)[l]{A3}}
\put(28,80){\makebox(1.75,2)[r]{\small 20}}\put(30.25,79){\makebox(4,2)[l]{A2}}
\put(28,82){\makebox(1.75,2)[r]{\small 19}}\put(30.25,81){\makebox(4,2)[l]{A1}}
\put(28,84){\makebox(1.75,2)[r]{\small 18}}\put(30.25,83){\makebox(4,2)[l]{A0}}
\put(28,86){\makebox(1.75,2)[r]{\small 17}}\put(30.25,85){\makebox(4,2)[l]{MUX}}
\put(28,88){\makebox(1.75,2)[r]{\small 16}}\put(30.25,87){\makebox(4,2)[l]{AEC}}
\put(28,90){\makebox(1.75,2)[r]{\small 2}}\put(30.25,89){\makebox(4,2)[l]{\overbar{RESET}}}
\put(38.25,92){\makebox(2,2)[l]{\small 1}}\put(36,94){\makebox(4,2){$\rm V_{DD}$}}
%
% The IC9 (74F32)
%
%% The frame and the pins
\thicklines
\put(50.5,64){\line(0,1){14}\line(1,0){7}\line(0,1){14}}\put(50.5,78){\line(1,0){7}}
\thinlines
\multiput(49.5,66)(0,2){6}{\line(1,0){1}}
\multiput(57.5,66)(0,2){6}{\line(1,0){1}}
\put(54,78){\vector(0,1){2}}
\put(53,62){\line(1,0){1}\line(0,1){2}\line(1,0){1}}
%% The pin numbers and the labels
\put(48.5,76){\makebox(1.75,2)[r]{\small 1}}\put(50.75,75){\makebox(2,2)[l]{A1}}
\put(48.5,74){\makebox(1.75,2)[r]{\small 4}}\put(50.75,73){\makebox(2,2)[l]{A2}}
\put(48.5,72){\makebox(1.75,2)[r]{\small 10}}\put(50.75,71){\makebox(2,2)[l]{A3}}
\put(48.5,70){\makebox(1.75,2)[r]{\small 13}}\put(50.75,69){\makebox(2,2)[l]{A4}}
\put(48.5,68){\makebox(1.75,2)[r]{\small 3}}\put(50.75,67){\makebox(2,2)[l]{C1}}
\put(48.5,66){\makebox(1.75,2)[r]{\small 6}}\put(50.75,65){\makebox(2,2)[l]{C2}}
\put(54.25,62){\makebox(2,2)[l]{\small 7}}\put(52,60){\makebox(4,2){$\rm V_{SS}$}}
\put(57.75,66){\makebox(2,2)[l]{\small 8}}\put(55.5,65){\makebox(1.75,2)[r]{C3}}
\put(57.75,68){\makebox(2,2)[l]{\small 9}}\put(55.5,67){\makebox(1.75,2)[r]{B3}}
\put(57.75,70){\makebox(2,2)[l]{\small 5}}\put(55.5,69){\makebox(1.75,2)[r]{B2}}
\put(57.75,72){\makebox(2,2)[l]{\small 11}}\put(55.5,71){\makebox(1.75,2)[r]{C4}}
\put(57.75,74){\makebox(2,2)[l]{\small 12}}\put(55.5,73){\makebox(1.75,2)[r]{B4}}
\put(57.75,76){\makebox(2,2)[l]{\small 2}}\put(55.5,75){\makebox(1.75,2)[r]{B1}}
\put(54.25,78){\makebox(2,2)[l]{\small 14}}\put(52,80){\makebox(4,2){$\rm V_{DD}$}}
%
% The U9 (74F32)
%
%% The frame and the pins
\thicklines
\put(64.5,64){\line(0,1){14}\line(1,0){7}\line(0,1){14}}\put(64.5,78){\line(1,0){7}}
\thinlines
\multiput(63.5,66)(0,2){6}{\line(1,0){1}}
\multiput(71.5,66)(0,2){6}{\line(1,0){1}}
\put(68,78){\vector(0,1){2}}
\put(67,62){\line(1,0){1}\line(0,1){2}\line(1,0){1}}
%% The pin numbers and the labels
\put(62.5,76){\makebox(1.75,2)[r]{\small 2}}\put(64.75,75){\makebox(2,2)[l]{B1}}
\put(62.5,74){\makebox(1.75,2)[r]{\small 12}}\put(64.75,73){\makebox(2,2)[l]{B4}}
\put(62.5,72){\makebox(1.75,2)[r]{\small 11}}\put(64.75,71){\makebox(2,2)[l]{C4}}
\put(62.5,70){\makebox(1.75,2)[r]{\small 5}}\put(64.75,69){\makebox(2,2)[l]{B2}}
\put(62.5,68){\makebox(1.75,2)[r]{\small 9}}\put(64.75,67){\makebox(2,2)[l]{B3}}
\put(62.5,66){\makebox(1.75,2)[r]{\small 8}}\put(64.75,65){\makebox(2,2)[l]{C3}}
\put(68.25,62){\makebox(2,2)[l]{\small 7}}\put(66,60){\makebox(4,2){$\rm V_{SS}$}}
\put(71.75,66){\makebox(2,2)[l]{\small 6}}\put(69.5,65){\makebox(1.75,2)[r]{C2}}
\put(71.75,68){\makebox(2,2)[l]{\small 3}}\put(69.5,67){\makebox(1.75,2)[r]{C1}}
\put(71.75,70){\makebox(2,2)[l]{\small 13}}\put(69.5,69){\makebox(1.75,2)[r]{A4}}
\put(71.75,72){\makebox(2,2)[l]{\small 10}}\put(69.5,71){\makebox(1.75,2)[r]{A3}}
\put(71.75,74){\makebox(2,2)[l]{\small 4}}\put(69.5,73){\makebox(1.75,2)[r]{A2}}
\put(71.75,76){\makebox(2,2)[l]{\small 1}}\put(69.5,75){\makebox(1.75,2)[r]{A1}}
\put(68.25,78){\makebox(2,2)[l]{\small 14}}\put(66,80){\makebox(4,2){$\rm V_{DD}$}}
%
% The U20 (4066)
%
%% The frame and the pins
\thicklines
\put(4,8){\line(0,1){10}\line(1,0){10}\line(0,1){10}}\put(4,18){\line(1,0){10}}
\thinlines
\multiput(6,7)(2,0){4}{\line(0,1){1}}\multiput(6,18)(2,0){4}{\line(0,1){1}}
\multiput(14,10)(0,2){4}{\line(1,0){1}}
\put(2,16){\vector(0,1){2}\line(1,0){2}}
\put(2,12){\line(1,0){2}}
\put(1,10){\line(1,0){1}\line(0,1){2}\line(1,0){1}}
%% The pin numbers and the labels
\put(4,6){\makebox(1.75,2)[r]{\small 13}}\put(5,8){\makebox(2,2){\small $\rm E_1$}}
\put(6,6){\makebox(1.75,2)[r]{\small 5}}\put(7,8){\makebox(2,2){\small $\rm E_2$}}
\put(8,6){\makebox(1.75,2)[r]{\small 6}}\put(9,8){\makebox(2,2){\small $\rm E_3$}}
\put(10,6){\makebox(1.75,2)[r]{\small 12}}\put(11,8){\makebox(2,2){\small $\rm E_4$}}
\put(4,18){\makebox(1.75,2)[r]{\small 1}}\put(5,16){\makebox(2,2){\small $\rm A_1$}}
\put(6,18){\makebox(1.75,2)[r]{\small 4}}\put(7,16){\makebox(2,2){\small $\rm A_2$}}
\put(8,18){\makebox(1.75,2)[r]{\small 8}}\put(9,16){\makebox(2,2){\small $\rm A_3$}}
\put(10,18){\makebox(1.75,2)[r]{\small 11}}\put(11,16){\makebox(2,2){\small $\rm A_4$}}
\put(14.1,10){\makebox(2,2)[l]{\small 2}}\put(12,9){\makebox(1.75,2)[r]{\small $\rm B_1$}}
\put(14.1,12){\makebox(2,2)[l]{\small 3}}\put(12,11){\makebox(1.75,2)[r]{\small $\rm B_2$}}
\put(14.1,14){\makebox(2,2)[l]{\small 9}}\put(12,13){\makebox(1.75,2)[r]{\small $\rm B_3$}}
\put(14.1,16){\makebox(2,2)[l]{\small 10}}\put(12,15){\makebox(1.75,2)[r]{\small $\rm B_4$}}
\put(2,12){\makebox(1.75,2)[r]{\small 7}}\put(4.25,11){\makebox(2,2)[l]{\small $\rm V_{SS}$}}
\put(2,14){\makebox(1.75,2)[r]{\small 14}}\put(4.25,15){\makebox(2,2)[l]{\small $\rm V_{DD}$}}
%
% The IC8 (4066)
%
%% The frame and the pins
\thicklines
\put(18,8){\line(0,1){10}\line(1,0){10}\line(0,1){10}}\put(18,18){\line(1,0){10}}
\thinlines
\multiput(20,7)(2,0){4}{\line(0,1){1}}\multiput(20,18)(2,0){4}{\line(0,1){1}}
\multiput(16,10)(0,2){4}{\line(1,0){2}}
\put(28,16){\line(1,0){2}\vector(0,1){2}}
\put(28,12){\line(1,0){2}}
\put(29,10){\line(1,0){1}\line(0,1){2}\line(1,0){1}}
%% The pin numbers and the labels
\put(18,6){\makebox(1.75,2)[r]{\small 13}}\put(19,8){\makebox(2,2){\small $\rm E_1$}}
\put(20,6){\makebox(1.75,2)[r]{\small 5}}\put(21,8){\makebox(2,2){\small $\rm E_2$}}
\put(22,6){\makebox(1.75,2)[r]{\small 6}}\put(23,8){\makebox(2,2){\small $\rm E_3$}}
\put(24,6){\makebox(1.75,2)[r]{\small 12}}\put(25,8){\makebox(2,2){\small $\rm E_4$}}
\put(18,18){\makebox(1.75,2)[r]{\small 1}}\put(19,16){\makebox(2,2){\small $\rm A_1$}}
\put(20,18){\makebox(1.75,2)[r]{\small 4}}\put(21,16){\makebox(2,2){\small $\rm A_2$}}
\put(22,18){\makebox(1.75,2)[r]{\small 8}}\put(23,16){\makebox(2,2){\small $\rm A_3$}}
\put(24,18){\makebox(1.75,2)[r]{\small 11}}\put(25,16){\makebox(2,2){\small $\rm A_4$}}
\put(16,10){\makebox(1.95,2)[r]{\small 2}}\put(18.25,9){\makebox(2,2)[l]{\small $\rm B_1$}}
\put(16,12){\makebox(1.95,2)[r]{\small 3}}\put(18.25,11){\makebox(2,2)[l]{\small $\rm B_2$}}
\put(16,14){\makebox(1.95,2)[r]{\small 9}}\put(18.25,13){\makebox(2,2)[l]{\small $\rm B_3$}}
\put(16,16){\makebox(1.95,2)[r]{\small 10}}\put(18.25,15){\makebox(2,2)[l]{\small $\rm B_4$}}
\put(28.25,12){\makebox(2,2)[l]{\small 7}}\put(26,11){\makebox(1.75,2)[r]{\small $\rm V_{SS}$}}
\put(28.25,14){\makebox(2,2)[l]{\small 14}}\put(26,15){\makebox(1.75,2)[r]{\small $\rm V_{DD}$}}
%
% The IC7 (74F00)
%
%% The operating voltages
\put(34,16){\vector(0,1){2}}\put(33,8){\line(1,0){1}\line(0,1){2}\line(1,0){1}}
\put(34.25,16){\makebox(2,2){14}}\put(34.25,8){\makebox(2,2){7}}
%% The ports N1 and N4
\multiput(44.25,13)(0,-6){2}{\circle{.5}}
\multiput(42,13)(0,-6){2}{\line(1,0){2}}
\multiput(46,11.5)(0,-6){2}{\line(0,1){3}}
\multiput(46,13)(0,-6){2}{\oval(3,3)[l]}
\put(46.05,6){\makebox(2,2)[l]{\small 2}}
\put(46.05,8){\makebox(2,2)[l]{\small 1}}
\put(42,7){\makebox(1.95,2)[r]{\small 3}}
\put(46.05,12){\makebox(2,2)[l]{\small 12}}
\put(46.05,14){\makebox(2,2)[l]{\small 13}}
\put(42,13){\makebox(1.95,2)[r]{\small 11}}
%% The ports N2 and N3
\multiput(28.25,6)(7,-1){2}{\circle{.5}}
\multiput(26,6)(7,-1){2}{\line(1,0){2}}
\multiput(30,4.5)(7,-1){2}{\line(0,1){3}}
\multiput(30,6)(7,-1){2}{\oval(3,3)[l]}
\put(30.05,5){\makebox(2,2)[l]{\small 5}}
\put(30.05,7){\makebox(2,2)[l]{\small 4}}
\put(26,6){\makebox(1.95,2)[r]{\small 6}}
\put(37.05,4){\makebox(2,2)[l]{\small 10}}
\put(37.05,6){\makebox(2,2)[l]{\small 9}}
\put(33,5){\makebox(1.95,2)[r]{\small 8}}
%
% The IC6 (74LS138)
%
%% The frame and the pins
\thicklines
\put(50,4){\line(0,1){20}\line(1,0){8}\line(0,1){20}}\put(50,24){\line(1,0){8}}
\thinlines
\multiput(49,6)(0,2){9}{\line(1,0){1}}\multiput(58,6)(0,2){2}{\line(1,0){1}}
\put(54,24){\vector(0,1){2}}\put(53,2){\line(1,0){1}\line(0,1){2}\line(1,0){1}}
%% The pin numbers and the labels
\put(48,22){\makebox(1.95,2)[r]{\small 1}}\put(50.25,21){\makebox(2,2)[l]{A}}
\put(48,20){\makebox(1.95,2)[r]{\small 2}}\put(50.25,19){\makebox(2,2)[l]{B}}
\put(48,18){\makebox(1.95,2)[r]{\small 3}}\put(50.25,17){\makebox(2,2)[l]{C}}
\put(48,16){\makebox(1.95,2)[r]{\small 15}}\put(50.25,15){\makebox(2,2)[l]{\overbar{Y0}}}
\put(48,14){\makebox(1.95,2)[r]{\small 14}}\put(50.25,13){\makebox(2,2)[l]{\overbar{Y1}}}
\put(48,12){\makebox(1.95,2)[r]{\small 13}}\put(50.25,11){\makebox(2,2)[l]{\overbar{Y2}}}
\put(48,10){\makebox(1.95,2)[r]{\small 12}}\put(50.25,9){\makebox(2,2)[l]{\overbar{Y3}}}
\put(48,8){\makebox(1.95,2)[r]{\small 11}}\put(50.25,7){\makebox(2,2)[l]{\overbar{Y4}}}
\put(48,6){\makebox(1.95,2)[r]{\small 10}}\put(50.25,5){\makebox(2,2)[l]{\overbar{Y5}}}
\put(54.25,2){\makebox(2,2)[l]{\small 8}}\put(52,0){\makebox(4,2){\small $\rm V_{SS}$}}
\put(58.1,6){\makebox(2,2)[l]{\small 9}}\put(56,5){\makebox(1.75,2)[r]{\overbar{Y6}}}
\put(58.1,8){\makebox(2,2)[l]{\small 7}}\put(56,7){\makebox(1.75,2)[r]{\overbar{Y7}}}
\put(58.1,18){\makebox(2,2)[l]{\small 6}}\put(56,17){\makebox(1.75,2)[r]{G1}}
\put(58.1,20){\makebox(2,2)[l]{\small 5}}\put(56,19){\makebox(1.75,2)[r]{\overbar{G2}}}
\put(58.1,22){\makebox(2,2)[l]{\small 4}}\put(56,21){\makebox(1.75,2)[r]{\overbar{G3}}}
\put(54.25,24){\makebox(2,2)[l]{\small 16}}\put(52,26){\makebox(4,2){\small $\rm V_{DD}$}}
%
% The U3 (74LS138)
%
%% The frame and the pins
\thicklines
\put(64,4){\line(0,1){20}\line(1,0){8}\line(0,1){20}}\put(64,24){\line(1,0){8}}
\thinlines
\multiput(72,6)(0,2){9}{\line(1,0){1}}\multiput(63,6)(0,2){2}{\line(1,0){1}}
\put(68,24){\vector(0,1){2}}\put(67,2){\line(1,0){1}\line(0,1){2}\line(1,0){1}}
%% The pin numbers and the labels
\put(72.1,22){\makebox(2,2)[l]{\small 1}}\put(70,21){\makebox(1.75,2)[r]{A}}
\put(72.1,20){\makebox(2,2)[l]{\small 2}}\put(70,19){\makebox(1.75,2)[r]{B}}
\put(72.1,18){\makebox(2,2)[l]{\small 3}}\put(70,17){\makebox(1.75,2)[r]{C}}
\put(72.1,16){\makebox(2,2)[l]{\small 15}}\put(70,15){\makebox(1.75,2)[r]{\overbar{Y0}}}
\put(72.1,14){\makebox(2,2)[l]{\small 14}}\put(70,13){\makebox(1.75,2)[r]{\overbar{Y1}}}
\put(72.1,12){\makebox(2,2)[l]{\small 13}}\put(70,11){\makebox(1.75,2)[r]{\overbar{Y2}}}
\put(72.1,10){\makebox(2,2)[l]{\small 12}}\put(70,9){\makebox(1.75,2)[r]{\overbar{Y3}}}
\put(72.1,8){\makebox(2,2)[l]{\small 11}}\put(70,7){\makebox(1.75,2)[r]{\overbar{Y4}}}
\put(72.1,6){\makebox(2,2)[l]{\small 10}}\put(70,5){\makebox(1.75,2)[r]{\overbar{Y5}}}
\put(68.25,2){\makebox(2,2)[l]{\small 8}}\put(66,0){\makebox(4,2){\small $\rm V_{SS}$}}
\put(62,6){\makebox(1.95,2)[r]{\small 9}}\put(64.25,5){\makebox(2,2)[l]{\overbar{Y6}}}
\put(62,8){\makebox(1.95,2)[r]{\small 7}}\put(64.25,7){\makebox(2,2)[l]{\overbar{Y7}}}
\put(62,18){\makebox(1.95,2)[r]{\small 6}}\put(64.25,17){\makebox(2,2)[l]{G1}}
\put(62,20){\makebox(1.95,2)[r]{\small 5}}\put(64.25,19){\makebox(2,2)[l]{\overbar{G2}}}
\put(62,22){\makebox(1.95,2)[r]{\small 4}}\put(64.25,21){\makebox(2,2)[l]{\overbar{G3}}}
\put(68.25,24){\makebox(2,2)[l]{\small 16}}\put(66,26){\makebox(4,2){\small $\rm V_{DD}$}}
%
% Other components
%
%% The serial resistors R3 and R4 (68R)
\multiput(50,47)(0,6){2}{\makebox(6,2){68~$\Omega$}}
\put(50,55){\framebox(6,2){\bf R3}}
\put(50,49){\framebox(6,2){\bf R4}}
%
% The connections
%
%% Between the MMUs
\multiput(20,26)(0,2){7}{\line(1,0){10}}
\multiput(20,42)(0,2){5}{\line(1,0){10}}
\multiput(20,54)(0,2){19}{\line(1,0){10}}
%% The IC9 (74F32)
\multiput(46,72)(0,2){2}{\line(1,0){4.5}}\multiput(48.25,72)(0,2){2}{\circle{0}}
\put(48.25,70){\line(0,1){2}\line(1,0){2.25}}
\put(48.25,76){\line(0,-1){2}\line(1,0){2.25}}
\multiput(57.5,66)(0,6){2}{\line(1,0){3.5}}\multiput(61,66)(0,6){2}{\circle{0}}
\multiput(57.5,68)(0,6){2}{\line(1,0){4.5}\line(0,-1){2}}\multiput(60,68)(0,6){2}{\circle{0}}
\multiput(57.5,70)(0,6){2}{\line(1,0){2.5}\line(0,-1){2}}
\multiput(62,66)(0,6){2}{\line(1,0){2.5}}
\put(49.5,56){\line(0,1){10}\line(1,0){.5}}
\put(48.25,68){\line(0,-1){18}\line(1,0){1.75}}\put(48.25,50){\line(1,0){1.75}}
\multiput(56,50)(0,6){2}{\line(1,0){2}}
\put(58,54.5){\framebox(12,3){\overbar{RAMCAS2}}}
\put(58,48.5){\framebox(12,3){\overbar{RAMCAS3}}}
%% The IC8 (4066)
\put(22,52){\line(0,-1){34}\line(1,0){8}}
\put(20,20){\line(0,-1){2}\line(1,0){2}}\put(22,20){\circle{0}}
\put(20,40){\line(1,0){4}\line(0,-1){22}}
\put(26,38){\circle{0}}\put(26,38){\line(0,-1){20}}
\put(16,14){\line(0,1){8}\line(1,0){2}}
\put(16,16){\circle{0}}\put(16,16){\line(1,0){2}}
\put(16,22){\line(1,0){12}\line(0,1){18}}\put(28,40){\line(1,0){2}}
\multiput(14,10)(0,2){2}{\line(1,0){4}}
%% The IC6 (74LS138)
\multiput(58,18)(0,2){3}{\line(1,0){6}}
\multiput(45,18)(0,2){3}{\line(1,0){5}}
\put(42,21.2){\framebox(3,1.6){A0}}
\put(42,19.2){\framebox(3,1.6){A1}}
\put(42,17.2){\framebox(3,1.6){A2}}
\put(42,15.2){\framebox(3,1.6){A3}}
\multiput(46,6)(0,6){2}{\line(1,0){4}}
\put(46,8){\line(1,0){2}\line(0,-1){8}}\put(48,6){\circle{0}}
\put(46,14){\line(1,0){2}\line(0,1){2}}\put(48,16){\line(1,0){2}}
%% The IC7 (74F00)
\put(20,4){\line(0,1){4}\line(1,0){12}\line(0,1){3}}\put(32,5){\circle{0}}
\put(30,5){\line(1,0){4}}\put(30,7){\line(1,0){2}}
\put(22,6){\line(0,1){2}\line(1,0){4}}
\put(24,0){\line(0,1){8}\line(1,0){24}}
\put(37,4){\line(1,0){3}\line(0,1){9}}\put(40,13){\line(1,0){2}}
\put(37,6){\line(1,0){2}\line(0,1){10}}\put(39,16){\line(1,0){3}}
\put(26,2){\line(0,1){6}\line(1,0){16}\line(0,1){5}}
\end{picture}
\end{center}
\caption{The schematics diagram for the MMU expansion logic.}
\label{MMUschematics}
\end{figure}

The biggest problem with this expansion is that the MOS~8722~MMU is a
custom chip from Commodore, and it is only used in the Commodore~128,
which has not been manufactured for ages. If you do not happen to have
a wreck C128 lying around, you can try ordering the chip from Jameco
Electronics. The chip shouldn't cost more than 10~USD. You can reach
them at:

\begin{tabular}{r l}
\\ {\em Orders (phone):} & 1-800-831-4242
\\ {\em Orders (fax):} & 1-800-237-6948
\\ {\em Fax (overseas):} & +1-415-592-2503
\\ {\em Mail:}
  & Jameco Electronics
\\& 1355 Shoreway Road
\\& Belmont, CA  94002
\\& U.S.A.
\end{tabular}

\begin{figure}[hbt]
\setlength{\unitlength}{1.5ex}
\begin{center}
\begin{picture}(26,48)(-5,0)
% Caption
\put(-5,48){\makebox(26,2){\bf MOS~8722~MMU}}
% The Dual-In-Line housing
\thicklines
\put(1,0){\line(0,1){48}\line(1,0){14}\line(0,1){48}}\put(1,48){\line(1,0){14}}
\put(8,48){\oval(2,2)[b]}\put(1.5,47.5){\circle{0}}
% The pins
\thinlines
\multiput(0,1)(0,2){24}{\line(1,0){1}}
\multiput(15,1)(0,2){24}{\line(1,0){1}}
% The pin numbers
\put(2,46){\makebox(2,2)[l]{1}}
\put(2,44){\makebox(2,2)[l]{2}}
\put(2,42){\makebox(2,2)[l]{3}}
\put(2,40){\makebox(2,2)[l]{4}}
\put(2,38){\makebox(2,2)[l]{5}}
\put(2,36){\makebox(2,2)[l]{6}}
\put(2,34){\makebox(2,2)[l]{7}}
\put(2,32){\makebox(2,2)[l]{8}}
\put(2,30){\makebox(2,2)[l]{9}}
\put(2,28){\makebox(2,2)[l]{10}}
\put(2,26){\makebox(2,2)[l]{11}}
\put(2,24){\makebox(2,2)[l]{12}}
\put(2,22){\makebox(2,2)[l]{13}}
\put(2,20){\makebox(2,2)[l]{14}}
\put(2,18){\makebox(2,2)[l]{15}}
\put(2,16){\makebox(2,2)[l]{16}}
\put(2,14){\makebox(2,2)[l]{17}}
\put(2,12){\makebox(2,2)[l]{18}}
\put(2,10){\makebox(2,2)[l]{19}}
\put(2,8){\makebox(2,2)[l]{20}}
\put(2,6){\makebox(2,2)[l]{21}}
\put(2,4){\makebox(2,2)[l]{22}}
\put(2,2){\makebox(2,2)[l]{23}}
\put(2,0){\makebox(2,2)[l]{24}}
\put(12,0){\makebox(2,2)[r]{25}}
\put(12,2){\makebox(2,2)[r]{26}}
\put(12,4){\makebox(2,2)[r]{27}}
\put(12,6){\makebox(2,2)[r]{28}}
\put(12,8){\makebox(2,2)[r]{29}}
\put(12,10){\makebox(2,2)[r]{30}}
\put(12,12){\makebox(2,2)[r]{31}}
\put(12,14){\makebox(2,2)[r]{32}}
\put(12,16){\makebox(2,2)[r]{33}}
\put(12,18){\makebox(2,2)[r]{34}}
\put(12,20){\makebox(2,2)[r]{35}}
\put(12,22){\makebox(2,2)[r]{36}}
\put(12,24){\makebox(2,2)[r]{37}}
\put(12,26){\makebox(2,2)[r]{38}}
\put(12,28){\makebox(2,2)[r]{39}}
\put(12,30){\makebox(2,2)[r]{40}}
\put(12,32){\makebox(2,2)[r]{41}}
\put(12,34){\makebox(2,2)[r]{42}}
\put(12,36){\makebox(2,2)[r]{43}}
\put(12,38){\makebox(2,2)[r]{44}}
\put(12,40){\makebox(2,2)[r]{45}}
\put(12,42){\makebox(2,2)[r]{46}}
\put(12,44){\makebox(2,2)[r]{47}}
\put(12,46){\makebox(2,2)[r]{48}}
% The descriptions
\put(-5,46){\makebox(5,2)[r]{$\rm V_{DD}$}}
\put(-5,44){\makebox(5,2)[r]{\overbar{RESET}}}
\put(-5,42){\makebox(5,2)[r]{TA15}}
\put(-5,40){\makebox(5,2)[r]{TA14}}
\put(-5,38){\makebox(5,2)[r]{TA13}}
\put(-5,36){\makebox(5,2)[r]{TA12}}
\put(-5,34){\makebox(5,2)[r]{TA11}}
\put(-5,32){\makebox(5,2)[r]{TA10}}
\put(-5,30){\makebox(5,2)[r]{TA9}}
\put(-5,28){\makebox(5,2)[r]{TA8}}
\put(-5,26){\makebox(5,2)[r]{\overbar{CAS1}}}
\put(-5,24){\makebox(5,2)[r]{\overbar{CAS0}}}
\put(-5,22){\makebox(5,2)[r]{MS2}}
\put(-5,20){\makebox(5,2)[r]{MS1}}
\put(-5,18){\makebox(5,2)[r]{MS0}}
\put(-5,16){\makebox(5,2)[r]{AEC}}
\put(-5,14){\makebox(5,2)[r]{MUX}}
\put(-5,12){\makebox(5,2)[r]{A0}}
\put(-5,10){\makebox(5,2)[r]{A1}}
\put(-5,8){\makebox(5,2)[r]{A2}}
\put(-5,6){\makebox(5,2)[r]{A3}}
\put(-5,4){\makebox(5,2)[r]{A5/A4}}
\put(-5,2){\makebox(5,2)[r]{A7/A6}}
\put(-5,0){\makebox(5,2)[r]{A8}}
\put(16,0){\makebox(5,2)[l]{A9}}
\put(16,2){\makebox(5,2)[l]{A10}}
\put(16,4){\makebox(5,2)[l]{A11}}
\put(16,6){\makebox(5,2)[l]{A12}}
\put(16,8){\makebox(5,2)[l]{A13}}
\put(16,10){\makebox(5,2)[l]{A14}}
\put(16,12){\makebox(5,2)[l]{A15}}
\put(16,14){\makebox(5,2)[l]{R/\overbar{W}}}
\put(16,16){\makebox(5,2)[l]{$\rm \Phi_{IN}$}}
\put(16,18){\makebox(5,2)[l]{$\rm V_{SS}$}}
\put(16,20){\makebox(5,2)[l]{D0}}
\put(16,22){\makebox(5,2)[l]{D1}}
\put(16,24){\makebox(5,2)[l]{D2}}
\put(16,26){\makebox(5,2)[l]{D3}}
\put(16,28){\makebox(5,2)[l]{D4}}
\put(16,30){\makebox(5,2)[l]{D5}}
\put(16,32){\makebox(5,2)[l]{D6}}
\put(16,34){\makebox(5,2)[l]{D7}}
\put(16,36){\makebox(5,2)[l]{\overbar{Z80EN}}}
\put(16,38){\makebox(5,2)[l]{\overbar{FSDIR}}}
\put(16,40){\makebox(5,2)[l]{\overbar{GAME}}}
\put(16,42){\makebox(5,2)[l]{\overbar{EXROM}}}
\put(16,44){\makebox(5,2)[l]{MS3}}
\put(16,46){\makebox(5,2)[l]{40/\overbar{80}}}
\end{picture}
\caption{The MOS~8722 Memory Management Unit}
\label{MMUpins}
\end{center}
\end{figure}

\begin{table}
\begin{center}
\begin{tabular}{|l|l|}
\hline
\multicolumn{2}{|c|}{\bf Electronic Components} \\ \hline
\multicolumn{1}{|c}{Symbol} & \multicolumn{1}{|c|}{Description} \\
\hline
IC5      & MOS 8722 \\
IC6      & 74LS138 \\
IC7      & 74F00 \\
IC8      & 4066 \\
IC9      & 74F32 \\
IC10--IC25 & 80256 or compatible \\
R3, R4   & $68~\Omega$ resistor \\
\hline
\hline
\multicolumn{2}{|c|}{\bf Other Parts} \\ \hline
\multicolumn{1}{|c}{Quantity} & \multicolumn{1}{|c|}{Quality} \\
\hline 
1 pc      & 14-pin socket \\
plenty of & connection wire \\
\hline
\end{tabular}
\end{center}
\caption{Parts list for the MMU expansion}
\end{table}

\begin{figure}[hbt]
\setlength{\unitlength}{1.5ex}
\begin{center}
\begin{picture}(53,16)(-3,0)
% Captions
\put(-5,16){\makebox(20,2){\bf 74LS138}}
\put(15,16){\makebox(20,2){\bf 74F00}}
\put(35,16){\makebox(20,2){\bf 4066}}
% The Dual-In-Line housings
\thicklines
\put(1,0){\line(0,1){16}\line(1,0){8}\line(0,1){16}}\put(1,16){\line(1,0){8}}
\multiput(21,2)(20,0){2}{\line(0,1){14}\line(1,0){8}\line(0,1){14}}
\multiput(21,16)(20,0){2}{\line(1,0){8}}
\multiput(5,16)(20,0){3}{\oval(2,2)[b]}\multiput(1.5,15.5)(20,0){3}{\circle{0}}
% The pins
\thinlines
\multiput(0,1)(0,2){8}{\line(1,0){1}}
\multiput(9,1)(0,2){8}{\line(1,0){1}}
\multiput(20,3)(0,2){7}{\line(1,0){1}}
\multiput(29,3)(0,2){7}{\line(1,0){1}}
\multiput(40,3)(0,2){7}{\line(1,0){1}}
\multiput(49,3)(0,2){7}{\line(1,0){1}}
% The pin numbers
\put(2,0){\makebox(2,2)[l]{8}}
\put(6,0){\makebox(2,2)[r]{9}}
\put(6,2){\makebox(2,2)[r]{10}}
\put(6,4){\makebox(2,2)[r]{11}}
\put(6,6){\makebox(2,2)[r]{12}}
\put(6,8){\makebox(2,2)[r]{13}}
\put(6,10){\makebox(2,2)[r]{14}}
\put(6,12){\makebox(2,2)[r]{15}}
\put(6,14){\makebox(2,2)[r]{16}}
\multiput(2,14)(20,0){3}{\makebox(2,2)[l]{1}}
\multiput(2,12)(20,0){3}{\makebox(2,2)[l]{2}}
\multiput(2,10)(20,0){3}{\makebox(2,2)[l]{3}}
\multiput(2,8)(20,0){3}{\makebox(2,2)[l]{4}}
\multiput(2,6)(20,0){3}{\makebox(2,2)[l]{5}}
\multiput(2,4)(20,0){3}{\makebox(2,2)[l]{6}}
\multiput(2,2)(20,0){3}{\makebox(2,2)[l]{7}}
\multiput(26,2)(20,0){2}{\makebox(2,2)[r]{8}}
\multiput(26,4)(20,0){2}{\makebox(2,2)[r]{9}}
\multiput(26,6)(20,0){2}{\makebox(2,2)[r]{10}}
\multiput(26,8)(20,0){2}{\makebox(2,2)[r]{11}}
\multiput(26,10)(20,0){2}{\makebox(2,2)[r]{12}}
\multiput(26,12)(20,0){2}{\makebox(2,2)[r]{13}}
\multiput(26,14)(20,0){2}{\makebox(2,2)[r]{14}}
% The descriptions
%% 74LS138
\put(-5,14){\makebox(5,2)[r]{A}}
\put(-5,12){\makebox(5,2)[r]{B}}
\put(-5,10){\makebox(5,2)[r]{C}}
\put(-5,8){\makebox(5,2)[r]{\overbar{G3}}}
\put(-5,6){\makebox(5,2)[r]{\overbar{G2}}}
\put(-5,4){\makebox(5,2)[r]{G1}}
\put(-5,2){\makebox(5,2)[r]{\overbar{Y7}}}
\put(-5,0){\makebox(5,2)[r]{$\rm V_{SS}$}}
\put(10,0){\makebox(5,2)[l]{\overbar{Y6}}}
\put(10,2){\makebox(5,2)[l]{\overbar{Y5}}}
\put(10,4){\makebox(5,2)[l]{\overbar{Y4}}}
\put(10,6){\makebox(5,2)[l]{\overbar{Y3}}}
\put(10,8){\makebox(5,2)[l]{\overbar{Y2}}}
\put(10,10){\makebox(5,2)[l]{\overbar{Y1}}}
\put(10,12){\makebox(5,2)[l]{\overbar{Y0}}}
\multiput(10,14)(20,0){3}{\makebox(5,2)[l]{$\rm V_{DD}$}}
%% 74F00
\multiput(15,2)(20,0){2}{\makebox(5,2)[r]{$\rm V_{SS}$}}
\multiput(20,5)(0,6){2}{\line(1,0){4.25}\line(0,1){3}}
\multiput(23.5,8)(0,6){2}{\circle{.5}}
\multiput(23.75,8)(0,6){2}{\line(1,0){.5}}
\multiput(20,5)(0,2){6}{\line(1,0){1.75}}
\multiput(21.75,6.5)(0,6){2}{\line(0,1){3}}
\multiput(21.75,8)(0,6){2}{\oval(3,3)[r]}
\multiput(25.75,3)(0,6){2}{\line(0,1){3}\line(1,0){4.25}}
\multiput(26.5,6)(0,6){2}{\circle{.5}}
\multiput(25.75,6)(0,6){2}{\line(1,0){.5}}
\multiput(28.25,3)(0,2){6}{\line(1,0){1.75}}
\multiput(28.25,4.5)(0,6){2}{\line(0,1){3}}
\multiput(28.25,6)(0,6){2}{\oval(3,3)[l]}
%% 4066
\put(35,14){\makebox(5,2)[r]{A1}}
\put(35,12){\makebox(5,2)[r]{B1}}
\put(35,10){\makebox(5,2)[r]{B2}}
\put(35,8){\makebox(5,2)[r]{A2}}
\put(35,6){\makebox(5,2)[r]{E2}}
\put(35,4){\makebox(5,2)[r]{E3}}
\put(50,2){\makebox(5,2)[l]{A3}}
\put(50,4){\makebox(5,2)[l]{B3}}
\put(50,6){\makebox(5,2)[l]{B4}}
\put(50,8){\makebox(5,2)[l]{A4}}
\put(50,10){\makebox(5,2)[l]{E4}}
\put(50,12){\makebox(5,2)[l]{E1}}
\end{picture}
\caption{The logic glue chips 74LS138, 74F00 and 4066}
\label{SmallPinouts}
\end{center}
\end{figure}

In Figure \ref{MMUschematics}, there is a wiring diagram for this
expansion. It is a bit tight, and needs some clarification. The U9 74F32
is a quad OR chip (each $\rm C_n = A_n \lor B_n$) that takes the
\overbar{CAS0} and \overbar{CAS1} outputs from the original MMU and lets
them through to the original memory chips as \overbar{RAMCAS0} and
\overbar{RAMCAS1} if and only if both the \overbar{CAS} output from the
video chip and the \overbar{CASENB} output from the PLA are active. IC9,
the 74F32 next to U9, ``hooks'' the \overbar{RAMCAS} outputs and lets
them through when the \overbar{CAS0} output of the new MMU is active,
that is, when the banks {\tt 0} or {\tt 1} are being accessed. The IC9
also generates the \overbar{CAS} signals for the two new memory banks,
\overbar{RAMCAS2} and \overbar{RAMCAS3}. The $68~\Omega$ resistors
protect the IC9, as the inputs of the DRAM chips are not fully TTL
compatible.

The logic glue at the lower edge of the picture take care of feeding
correct values to the new MMU's data leads D6 and D0. See Section
\ref{MMUinterface} for a complete description. The IC8 4066 takes the
data lines D0, D1, D6 and D7 from the system bus and feeds two of them to
the new MMU's data lines D0 and D6 at a time. In my implementation the D0
and D1 lines come from the U20 4066 and the remaining two data leads from
the original MMU. The U20 4066 is not really needed at all, as the same
lines are on the original MMU, but I chose it as it was easy to
piggy-back.

On the lower right corner is U3, a 74LS138 which takes care of producing
the \overbar{CS} (Chip Select) signals for the address ranges
{\tt\$D400}--{\tt\$DBFF} and {\tt\$DC00}--{\tt\$DFFF}. The IC6 does not
actually need any signals from it, not even the \overbar{IOCS} that is on
the contact \overbar{G2}, but it was easier to piggy-back so. If you
build a daughter board for this expansion too, you can wire the IC6's G1
to +5~V and the \overbar{G2} and \overbar{G3} to ground. The IC6 together
with the IC7, a quad Negative-AND chip, inputs the four lowmost address
bus bits and produces the Enable signals for the IC8 4066.

\subsubsection{Realizing the processor bus interface}

First bend up the pins 3--15, 35 and 41 of the new 8722~MMU chip (IC5)
aside. Bend the rest of the pins slightly to the opposite direction so
that they are perpendicular to the surface of the chip. If the old MMU
is in socket, pop it off. Push the new MMU on the back of the old one.
Solder the pins together, but be careful not to heat the chips too
much. Now you can insert the MMU pair to the socket.

After wiring those pins, you must build the logic for interfacing the
system data bus to the new MMU. Locate U3, 74LS138, it is to the left of
the processor (U6, 8502). Take another 74LS138 (IC6) and bend its pins
1--3, 7 and 9--15 aside. Solder the rest of the pins to corresponding U3
pins. Connect the pins 1--3 of the new chip to the processor's pins 7--9,
respectively.

Before connecting the IC6's required outputs, you have to solder IC7 and
IC8 on the board. First locate U20, the 4066 to the right of the RF
shield covering the video circuitry. Get a new 4066 (IC8) and bend its
pins 1, 4--6 and 8--13 to the side and solder the four downwards pointing
pins to the U20. Wire the pins 1 and 4 together and connect them to the
new MMU's pin~35, the data lead D0. Similarly, connect the pins 9 and 10
together, and solder them to the topmost MMU's pin~41, D6. Solder the
IC8's pins 8 and 11 to the system data bus lines D6 and D7, respectively.
They are available in the original MMU's pins 41 and 42. It is a good
idea to locate through-put places for these signals and solder the wires
there.

The next chip to be mounted is IC7, the 74F00. A good place for it is the
14-pin chip next to the IC6 and the processor. Leave only the pins 7 and
14 down and solder them to the chip on the motherboard. Connect the pins
13 and 12 from the 74F00 to the IC6's pins 15 and 13, and connect the
74F00's pins 11 and 10 together. Then solder the pin 9 to the 8502's
pin~10, A3. Solder the IC7's pin~8 to its own pins 4 and 5, and connect
it also to the IC8 4066's pin~13. Connect the IC7's pin~6 to the IC8's
pin~5. Lead the 74LS138's pin~10 to the 4066's pin~6 and to the 74F00's
pins 1 and 2. Lead the 74F00's pin~3 to the 4066's pin~12.

After all these piggy-backings, it is wise to check if the computer
powers up any more. If not, check the solderings. When I built this
second version of the MMU expansion, I swapped the 4066 pins 9 and 10
by mistake, which resulted in a miserably black screen each time I
desperately tried to power the computer up.

\subsubsection{Adding the new memory banking signals}

If the first stage succeeded, you can build the new logic for deriving
the \overbar{CAS} signals for the two new RAM banks. Locate U9 (74F32)
and lift it on a socket, if it was directly soldered to the system board.
If the computer works after this operation, you can continue with the
piggy-backing. Take a new 74F32 (IC9) and bend its all pins except 7, 9,
12 and 14 to the side. Bend the pins 8 and 11 of the old 74F32 up, so
that they can be connected to the IC9's pins 9 and 12, respectively.
Connect the pins 7 and 14, too. Solder a short length of stiff uni-strand
wire to the new 74F32's pins 8 and 11, in order that these pins reach the
socket on the motherboard. Connect the pin~12 of the new MMU to the IC9's
pins 13 and 10.

Now the computer should work just as earlier, except that when you try to
access the banks {\tt 2} or {\tt 3}, the processor will read randomly
changing garbage. You can verify this by moving the cursor to the top
left-hand corner of the screen and typing ``{\tt M~20400}'' or
``{\tt M~30400}'' in the machine language monitor a couple of times.

To generate the signals \overbar{RAMCAS2} and \overbar{RAMCAS3}, connect
the topmost MMU's pin~11 to the IC9's pins 1 and 4, and solder the new
74F00's pins 2 and 12 as well as the pins 5 and 9 together. Then mount R3
and R4, the $68~\Omega$ resistors to the new 74F00's pins 6 and 3. On
their free ends will be the \overbar{RAMCAS2} and \overbar{RAMCAS3}
signals, respectively.

\subsubsection{Soldering the memory chips}

After ensuring that the computer works, you can prepare for the final
step. Take the sixteen memory chips (4164's or similar if you are aiming
to the 256~kB memory expansion; 41256's or similar for the 1024~kB
expansion) and bend their pins~15 (\overbar{CAS}) up. Solder the
remaining pins on top of the sixteen memory chips on the motherboard.
Then combine the \overbar{CAS} signals of the eight new memory chips at
the front edge of the system board and connect them to R3 or R4.
Similarly, connect the pins~15 of the remaining memory chips and wire
them to the remaining $68~\Omega$ resistor.

Power the computer up again and pray until it works. If you can access
the banks {\tt 2} and {\tt 3} as expected, congratulations! When
re-assembling the chassis, be very careful with the RF shield.
Especially measure that the \overbar{CAS} signals for the new memory
banks have no contact with the shield.

\section{Using the expansion}
\subsection{The operation of the block switcher}

There are four new micro chips in the PIA expansion. The most important
of them is the PIA chip MC~6821, which holds the values of the block
selections. The PIA has two 8-bit ports set up in the addresses
{\tt 57280} and {\tt 57282}. The upper and lower four bits (nybbles) of
each port determine which 16~kB block is mapped to each 16~kB segment of
the processor's address space. IC2 and IC3 participate in forming the
memory block control signals.

There is a chip equivalent to the PIA even in Commodore's own 6500
series, but it is not suitable for this connection, as it is not TTL
compatible. The 6821 from Motorola 6800 series, which contains also
processors reminding those in the CSG\footnote{Commodore Semiconductor
Group; former Mostek or MOS Technologies} 6500 and 8500 series, is bus
compatible and suitable for this purpose.

Commodore~128 asserts the 16 bit addresses to the original 64~kb chips
in two parts. First it asserts the lower eight bits, then the higher
eight. The 256~kb chips require two additional address bits, so the
chips are given nine bits at a time. Due to this address multiplexing,
the block selection bits cannot be directly input to the memory chips,
but they must be lead through the multiplexer circuitry of IC2, IC3 and
U14.

IC4 contributes to the operation during power-up. It ensures that the
C128 gets reasonable memory blocks to its different segments. In the
beginning the segments are filled with four upmost memory blocks.

\subsubsection{PIA's location in address space}

The PIA's data bus and E, \overbar{RESET} and R/\overbar{W} signals have
been connected directly to the 6526 chip. Similarly are the RS0 and the
RS1, which select a PIA register, connected to A0 and A1.

The I/O block decoder (U3) tells us when the second I/O block is
selected. This block resides in the area {\tt\$DF00}--{\tt\$DFFF}. The
signal \overbar{I/O2} is connected to the PIA's chip selection pin
\overbar{CS}, and it forms most of its addressing. The address line A7
limit PIA's area in I/O2 to {\tt\$DF80}--{\tt\$DFFF}, because it will
be tied to the CS pin.

\subsubsection{Block selection}

As the address space has been divided to four segments of 16~kB, the A14
and A15 cannot be lead directly to the memory chips, but they participate
in the block selection. These two address bits determine which of the
four blocks is in use. For each segment, the PIA ports tell which memory
block to map. Original A14 and A15 are connected to IC2 and IC3, which
select the right output lines of PIA. For each 16~kB segment there are 4
output lines which form the block address for the segment.

IC2 selects two lowest bits of the block address and feeds them to the
address multiplexer chip U14 as B14 and B15. They are practically
equivalent to the A14 and A15 signals. After the address bits A0--A7
have been asserted during the first addressing cycle, IC2 asserts B14
and B15 during the second (CAS) cycle.

The 256~kb memory chips still need two extra address bits. The expansion
must multiplex them with IC3, which is a `one-of-eight' multiplexer. Its
eight inputs are tied to the two upmost bits of the four block addresses.
A14 and A15 are connected to the IC3, but it needs yet another control
signal to handle all eight input bits. This signal is MUX, which controls
multiplexing other address bits (MA0--MA7) as well.

While the MUX signal is low and the memory chips are fed the lowest bits
(A0--A7) of the address, the IC3 selects the third bit of the block
address determined by A14 and A15. This bit is called address bit A16,
and it is asserted to the `extra' address line MA8 simultaneously with
the lowmost bits. When MUX is high, the upper address bits are fed, and
IC3 selects the fourth bit of the block address determined by A14 and
A15. It corresponds to the address bit A17 and is fed through the same
MA8 with all the other upmost bits.

When the video chip accesses the bus, the address and data lines from the
processors are in high-impedance state, driven to logical `{\tt 1}' level
with very weak current, so that the video chip can change their state
easily. As the address lines A14 and A15 (or actually TA14 and TA15 in
the C128) are not connected to the VIC-IIe, they remain as logical
`{\tt 1}' whenever the video chip has the bus. Thus, the switcher logic
`thinks' that the address range {\tt\$C000}--{\tt\$FFFF} is being
addressed, and it selects the block for that segment also for the
VIC-IIe.

The resistor on the MA8 line protects the IC3, because the inputs of
dynamic memories are not fully TTL compatible.

\subsubsection{Interfacing the second MMU}
\label{MMUinterface}

The new MMU must be fooled so that it mistakes the memory bank~{\tt 2}
for bank~{\tt 1}. This can be done by connecting its data bit D6 to the
system data line D7 whenever the RAM Configuration Register (location
{\tt\$D506}\footnote{See Table \ref{MMU_RCR}.}) or any of the
Configuration Registers ({\tt\$D500}--{\tt\$D504} and {\tt\$FF00}--%
{\tt\$FF04}\footnote{See Table \ref{MMU_CR}.}) are being accessed. In
addition to this, the page relocation registers must be taken into
consideration, or you could relocate the processor pages 0 and 1 only to
banks {\tt 0} or {\tt 3}. For this reason, the MMU data line D1 must be
connected to system data line D0 when the locations {\tt\$D508} or
{\tt\$D50A} are being accessed. There is a commercial 256~kB or 512~kB
expansion for the C128 that does not take care of this.

Actually the logic rules can be relaxed, and the MMU pin D6 can be
connected to system D7 for most time. The only register that needs the D6
line to be connected to system D6 is the Mode Configuration Register
({\tt\$D505}).\footnote{See Table \ref{MMU_MCR}.}

Connecting the D1 and D6 pins is performed by three chips: 74LS138, 74F00
and 4066. Consult Figure \ref{SmallPinouts} for their pinouts. The
74LS138 inputs a 3-digit binary number through its A, B and C pins and
converts it to an octal digit by activating one of its eight output lines
\overbar{${\rm Y}_n$}, provided that the chip has been selected with the
G inputs. The 74F00 is a quad Negative-AND chip, and the 4066 is a quad
analog switch. It connects its ${\rm A}_n$ and ${\rm B}_n$ contacts
together whenever the respective ${\rm E}_n$ pin is in the logical `{\tt
1}' state. The IC6 74LS138 and the IC7 74F00 generate the E signals for
the IC8 4066 from the system address lines A0--A3.

\subsubsection{Startup settings for the PIA expansion}
\label{InitialState}

In order to enable the operation of the machine, each of the four
segments must be mapped to a unique memory block. The Commodore~64
Kernal tests the lowmost continuous area of writeable memory and would
hang up, if the same block was mapped to both {\tt\$0000} and to
{\tt\$4000}, for instance. Modifying the startup routines would cure
this problem, but in that case the Kernal ROM chip should be changed.
Also the C128 Kernal would need some patching, if you don't want to run
any initializer program every time you start the computer up.

The bootup state can be achieved otherwise. The \overbar{RESET} signal
sets all the PIA port lines to inputs. As input a line has an impedance
of several megaohms. A TTL chip reads such a signal as a logical `{\tt
1}'. IC4 can force four block selection pins (PA0, PA1, PA5 and PB0) low,
so that the memory segments of C64 point to the four upmost memory blocks
in ascending order. The port~A contains the bits {\tt 1101~1100} and the
port~B {\tt 1111~1110}. As the IC4 has open collector outputs, it doesn't
disturb the port's operation when outputting high state. That is why the
initialization routines\footnote{See Section~\ref{MemoryInit}.} write the
value {\tt 52} to the address {\tt 57281}, which forces the IC4 outputs
high by lowering the CA2 line.

\subsection{Segmented memory}

The address space of Commodore~128 consists of four 16~kB segments which
are at the address ranges {\tt\$0000}--{\tt\$3FFF}, {\tt\$4000}--{\tt\$7FFF},
{\tt\$8000}--{\tt\$BFFF} and {\tt\$C000}--{\tt\$FFFF}. A PIA expanded
C128 uses the topmost four 16~kB blocks of each bank after startup. It
considers them as its whole world and does not know anything of the other
memory blocks. Figure~\ref{MemoryMap} describes the situation. A total of
twelve memory blocks of each memory bank are left out of the C128's world.

With expanded memory we can cheat the C128 by writing a suitable number
to a known address, in order to make it consider the lowmost block as the
second segment, for example. Then all operation that the C128 does at the
second segment's area alter in fact the lowmost block, although the
computer has no idea of it. This is the idea behind the whole PIA
expansion circuit.

What is the benefit of it? The second segment (segment~{\tt 1}) is
actually a good example of the function, because it resides in the middle
of the RAM reserved for C64 BASIC programs. If we make a little C64 BASIC
program that holds an array exactly in the third segment, we can switch
another memory block to that area while the program is running, and we
have another 16 kilobytes to expand our table. In this manner all unused
memory blocks ($12 \times 16$ kilobytes) of the memory bank selected for
the C64 mode ({\tt 0} by default) can be taken in use, and the memory is
able to hold enormous arrays, which can be accessed simply by switching
the memory block. See Example~\ref{BigArray} for an example of this
technique.

Another and more useful way to exploit the extra blocks is to use them
as a RAM disk. A RAM disk means that you can copy even a whole disk to
these blocks and consider it as a new disk drive, from which you can load
program and data at a very fast speed. For a RAM disk you need a smart
program that redirects disk commands and executes them on the expanded
memory.\footnote{See Section~\ref{RAMdisk}.}

\subsection{Critical addresses for the PIA expansion}

The critical addresses of the device are {\tt 57216}--{\tt 57343}
({\tt\$DF80}--{\tt\$DFFF}). There is the PIA chip to which you {\tt
POKE} the values to switch memory blocks. The PIA does not have 128
registers, as one might think. There are sixteen copies of its 4
addresses in that memory area. For instance, the addresses {\tt 57216},
{\tt 57284}, {\tt 57288} and {\tt 57340} are equivalent to each other.

{\tt 57280} is a memory place whose lowmost four bits (bits~0--3, low
nybble) determine, which of the sixteen memory blocks is accessed
through the lowmost segment (segment~{\tt 0}) of Commodore~128. The
upper four bits (bits 4--7, high nybble) specify, which of the blocks
show up at the second segment (segment~{\tt 1}). In a similar manner the
low nybble of the address {\tt 57282} determines which block resides at
segment~{\tt 2}, and the high nybble tells the block addressed via the
upmost segment.

These addresses have even another function. They can act as data
direction registers as well, i.e. tell if the port lines are inputs or
outputs. However, this application uses only some of the PIA's
characteristics. For normal operation, all the port lines should be set
to outputs. The function of these addresses depend on the bit~2 of the
next address. For instance, the function of {\tt 57280} is defined with
the address {\tt 57281}. If you {\tt POKE} there a value with its third
bit set, the values written to {\tt 57280} will go to the data direction
register. Inputs have the corresponding data direction register bits
reset, and outputs have them set. See Tables \ref{DFC0}--\ref{DFC3} for
a complete description of PIA registers.

\pagebreak
\subsection{Initializing the PIA expansion}
\label{MemoryInit}

The second MMU, if any, does not need any initialization. In contrary to
that, the PIA does. Before using that expansion memory, you have to
first initialize the PIA. Every time when a \overbar{RESET} is issued,
the PIA registers change to the default state.\footnote{See
Section~\ref{InitialState}.} In the beginning of your program you will
initialize the PIA registers so that the default block division of
memory remains:

\medskip
\begin{tt}
\begin{tabular}{l l l}
pia & .equ \$DFC0
\\
\\ & LDA pia+1 & ; Select Peripheral Registers
\\ & ORA \#4
\\ & STA pia+1
\\ & TAX
\\ & LDA pia+3
\\ & ORA \#4
\\ & STA pia+3
\\ & TAY
\\
\\ & LDA \#\$FE & ; Set the default memory block data
\\ & STA pia
\\ & LDA \#\$DC
\\ & STA pia+2
\\
\\ & TXA        & ; Select Data Direction Registers
\\ & AND \#\$FD
\\ & STA pia+1
\\ & TYA
\\ & AND \#\$FD
\\ & STA pia+3
\\
\\ & LDA \#\$FF & ; Set the ports to output
\\ & STA pia
\\ & STA pia+2
\\
\\ & TXA
\\ & AND \#\$C7
\\ & ORA \#\$30 & ; Set CA1 and
\\ & STA pia+1  & ; select Peripheral Registers
\\ & STY pia+3
\end{tabular}
\end{tt}
\medskip

\pagebreak

You may want to use an array instead. That will save both space and
processing time but lose generality. Someone may have CB1 or CB2 in
use,\footnote {See Section~\ref{Expanding}.} and changing all the command
register bits causes side effects on these pins. Anyway, here is a BASIC
example of using an initialization table:

\begin{quote}
\begin{verbatim}
10 PIA=57280
20 FOR I=11 to 1 STEP -1:READ A:POKE PIA+I,A:NEXT
30 DATA 4,254,4,220,0,255,0,255,4,254,52
\end{verbatim}
\end{quote}

Many Commodore~64 games do not like any extra hardware in the area
{\tt\$DE00}--{\tt\$DFFF}, as it is used by many ``freezer'' cartridges
and alike. If you need to use such software with the memory expansion,
you can completely disable the PIA from the address space until a system
\overbar{RESET} occurs. To do this, change the last {\tt DATA} value on
the line {\tt 30} from {\tt 52} to {\tt 53}. By the way, the PIA
expansion can be easily enhanced to be the most powerful freezer
cartridge. See Section \ref{Freezer} if you are interested in this.

\subsection{Programming the PIA in machine language}

Think it in hexadecimal numbers. There are sixteen memory blocks,
numbered from {\tt 0} to {\tt F}. The address {\tt\$DFC0} holds two
hexadecimal digits. The less significant digit, the one at right,
selects the memory block for the segment~{\tt 0} ({\tt\$0000}--%
{\tt\$3FFF}), whereas the other digit is for segment~{\tt 1}. The other
important PIA address, {\tt\$DFC2}, selects the blocks for segments
{\tt 2} and {\tt 3} with is low and high nybble, respectively.

For instance, if you want to switch block~{\tt E} ({\tt\$38000}--%
{\tt\$3BFFF}) to segment~{\tt 1}, initialize the PIA and execute the
following. Note that your program must run outside segment~{\tt 1}
({\tt\$4000}--{\tt\$7FFF}), or otherwise the next instruction will be
fetched from the new block, thus probably crashing the processor.

\medskip
\begin{tt}
\begin{tabular}{l l l}
pia & .equ \$DFC0
\\
\\ & LDA pia & ; Segments 0 and 1
\\ & AND \#\$0F & ; Preserve segment~0
\\ & ORA \#\$E0 & ; Select block~E for segment~1
\\ & STA pia
\end{tabular}
\end{tt}
\medskip

If you used our initialization routine before this, the memory areas
{\tt\$4000}--{\tt\$7FFF} and {\tt\$8000}--{\tt\$BFFF} should now mirror
each other. This is an easy way to peek under ROMs and I/O with a simple
C64 mode machine language monitor that does not play with the 8502's I/O
registers to switch ROMs and I/O temporarily out. Also, this technique
can be used in the C128 machine language monitor to access the lowest
4~kB of other memory banks than {\tt 0}.%
\footnote{

  The built-in monitor for the C128 mode ignores the bank address when
  reading from the addresses {\tt\$0000}--{\tt\$03FF}, and reads the data
  always from bank {\tt 0}. You can work this around by mapping some
  other address range, like {\tt\$C000}--{\tt\$FFFF}, to the same block
  that the segment~{\tt 0} uses. Then you can read from, say, {\tt\$0000}
  in bank~{\tt 2}, by issuing the command {\tt M~2C000}.
}

\subsubsection{An exception: video memory}

As the video chip's address bus is only fourteen bits wide, it can access
only sixteen kilobytes directly. The two additional lines needed to
address 64~kB are provided by the second CIA. Its lines PA1 and PA0 are
the inverse of the VIC-IIe's address lines VA15 and VA14. The video RAM
bank is selected with the two upmost bits of the MMU register
{\tt\$D506},\footnote{See Table \ref{MMU_RCR}.} and it does not
necessarily need to be equal with the processor bank.

The VIC-IIe needs another two address lines to see full 256~kB of the
selected RAM bank. The PIA lines PB7 and PB6 (the uppest two bits of
{\tt\$DFC2}) serve as VA17 and VA16. So, the VIC-IIe memory does not
necessarily have to be accessible to 8502, but there is a restriction:
As the block selector for the upmost segment uses the same two lines,
both the VIC block and the block for segment~{\tt 3} cannot be chosen
freely.

For instance, if you want the VIC to `see' its RAM at {\tt\$04000}, the
lines VA17--VA14 must be `{\tt 0001}'. You can select only blocks {\tt
0}--{\tt 3} for segment~{\tt 3} to fulfill this condition. Let's assume
that you want block~{\tt 2} to be mapped there:

\medskip
\begin{tt}
\begin{tabular}{l l l}
cia2 & .equ \$DD00 \\
pia  & .equ \$DFC0
\\
\\ & LDA cia2+1 & ; First set the CIA2 lines
\\ & ORA \#\$03 & ; PA0 and PA1 to output.
\\ & STA cia2+1
\\
\\ & LDA cia2   & ; Then set PA1 and reset PA0.
\\ & AND \#\$FC & ; Remember, the lines VA15 and VA14
\\ & ORA \#\$02 & ; are the inverse of them.
\\ 
\\ & LDA pia+2  & ; Segments 2 and 3
\\ & AND \#\$0F & ; Preserve segment~2
\\ & ORA \#\$20 & ; Select block~2 for segment~3
\\ & STA pia+2
\end{tabular}
\end{tt}
\medskip

If you want the video bank selection to work exactly like in a stock
computer, you have four alternative memory block configurations. The
addresses {\tt\$DFC2} and {\tt\$DFC0} must contain one of the following
bytes: {\tt\$FE} and {\tt\$DC}, {\tt\$BA} and {\tt\$98}, {\tt\$76} and
{\tt\$54}, or {\tt\$32} and {\tt\$10}. You can use the expansion to
debug or examine programs that occupy full 64 or 128 kilobytes of normal
memory. When you issue a \overbar{RESET}, the program's memory will
remain totally unaltered, if it is outside the topmost four blocks.
There is no need for a `freezer' cartridge,\footnote{See Section
\ref{Freezer}.} and I'm pretty sure that such cartridges do not even
exist for the C128 mode.

\begin{table}
\begin{center}
\begin{tabular}{|c|l|}
\hline
\multicolumn{2}{|c|}{\bf Peripheral Register A} \\ 
\multicolumn{2}{|c|}{\em (Peripheral Lines PA7--PA0)} \\ \hline
Bits & Description \\ \hline
7--4 & Block Selection, Segment~{\tt 1} \\
3--0 & Block Selection, Segment~{\tt 0} \\
\hline
\hline
\multicolumn{2}{|c|}{\bf Data Direction Register A} \\ \hline
Bits & Description \\ \hline
7--0 & Data Direction of Peripheral Lines PA7--PA0 \\
& \parbox{4in}{\small\smallskip When a bit is set, its corresponding Port~A 
line is an output. Otherwise it is an input.\smallskip} \\ \hline
\end{tabular}
\end{center}
\caption{The PIA address {\tt\$DFC0} ({\tt 57280})}
\label{DFC0}
\end{table}

\begin{table}
\begin{center}
\begin{tabular}{|c|c l|}
\hline
\multicolumn{3}{|c|}{\bf Control Register A} \\ \hline
Bit(s) & \multicolumn{2}{l|}{Description} \\ \hline

 7 & \multicolumn{2}{l|}{IRQA1 Interrupt Flag} \\
& \multicolumn{2}{l|}{\parbox{4in}{\small\smallskip
Goes high on active transition of CA1; 
Automatically cleared by MPU read of Peripheral Register~A.
May also be cleared by hardware \overbar{RESET}.\smallskip}} \\ \hline

 6 & \multicolumn{2}{l|}{IRQA2 Interrupt Flag} \\
& \multicolumn{2}{l|}{\parbox{4in}{\small\smallskip When CA2 is an input, 
IRQA2 goes high on active transition of CA2; 
Automatically cleared by MPU read of Peripheral Register~A. 
May also be cleared by hardware \overbar{RESET}.\smallskip}} \\ \hline

 5--3 & \multicolumn{2}{l|}{CA2 Control} \\
& {\tt 00x} & Input, triggered on falling edge \\
& {\tt 01x} & Input, triggered on rising edge \\
&& {\parbox{3.6in}{\small\smallskip
    When {\tt x} is {\tt 1}, \overbar{IRQA} Interrupts 
    by CA2 active transition are enabled.\smallskip}} \\
& {\tt 10x} & Output, Read Strobe for Peripheral Register~A \\
&& {\parbox{3.6in}{\small\smallskip
    CA2 goes low on first high-to-low E transition following a read of
    Peripheral Register~A. When {\tt x} is {\tt 0}, it remains low until
    next active CA1 transition. When {\tt x} is {\tt 1}, CA2 remains low
    for one E cycle.\smallskip}} \\
& {\tt 110} & Reset CA2 \\
& {\tt 111} & Set CA2 \\ \hline

 2 & \multicolumn{2}{l|}{Register in address {\tt\$DFC0}} \\
& {\tt 0} & Data Direction Register \\
& {\tt 1} & Peripheral Register \\ \hline

 1 & \multicolumn{2}{l|}{Determine Active CA1 Transition} \\
& {\tt 0} & IRQA1 set by high-to-low transition on CA1 \\
& {\tt 1} & IRQA1 set by low-to-high transition on CA1 \\ \hline

 0 & \multicolumn{2}{l|}{CA1 Interrupt Request Enable/Disable} \\
& {\tt 0} & Disable \overbar{IRQA} Interrupt by CA1 active transition. \\
& {\tt 1} & Enable \overbar{IRQA} Interrupt by CA1 active transition. \\ \hline
\end{tabular}
\end{center}
\caption{The PIA address {\tt\$DFC1} ({\tt 57281})}
\label{DFC1}
\end{table}

\begin{table}
\begin{center}
\begin{tabular}{|c|l|}
\hline
\multicolumn{2}{|c|}{\bf Peripheral Register B} \\ 
\multicolumn{2}{|c|}{\em (Peripheral Lines PB7--PB0)} \\ \hline
Bits & Description \\ \hline
7--4 & Block Selection, Segment~{\tt 3} \\
3--0 & Block Selection, Segment~{\tt 2} \\
\hline
\hline
\multicolumn{2}{|c|}{\bf Data Direction Register B} \\ \hline
Bits & Description \\ \hline
7--0 & Data Direction of Peripheral Lines PB7--PB0 \\
& \parbox{4in}{\small\smallskip When a bit is set, its corresponding Port~B 
line is an output. Otherwise it is an input.\smallskip} \\ \hline
\end{tabular}
\end{center}
\caption{The PIA address {\tt\$DFC2} ({\tt 57282})}
\label{DFC2}
\end{table}

\begin{table}
\begin{center}
\begin{tabular}{|c|c l|}
\hline
\multicolumn{3}{|c|}{\bf Control Register B} \\ \hline
Bit(s) & \multicolumn{2}{l|}{Description} \\ \hline

 7 & \multicolumn{2}{l|}{IRQB1 Interrupt Flag} \\
& \multicolumn{2}{l|}{\parbox{4in}{\small\smallskip
Goes high on active transition of CB1;
Automatically cleared by MPU read of Peripheral Register~B.
May also be cleared by hardware \overbar{RESET}.\smallskip}} \\ \hline

 6 & \multicolumn{2}{l|}{IRQB2 Interrupt Flag} \\
& \multicolumn{2}{l|}{\parbox{4in}{\small\smallskip When CB2 is an input, 
IRQB2 goes high on active transition of CB2; 
Automatically cleared by MPU read of Peripheral Register~B. 
May also be cleared by hardware \overbar{RESET}.\smallskip}} \\ \hline

 5--3 & \multicolumn{2}{l|}{CB2 Control} \\
& {\tt 00x} & Input, triggered on falling edge \\
& {\tt 01x} & Input, triggered on rising edge \\
&& {\parbox{3.6in}{\small\smallskip
    When {\tt x} is {\tt 1}, \overbar{IRQB} Interrupts 
    by CB2 active transition are enabled.\smallskip}} \\
& {\tt 10x} & Output, Read Strobe for Peripheral Register~B \\
&& {\parbox{3.6in}{\small\smallskip
    CB2 goes low on first high-to-low E transition following a read of
    Peripheral Register~B. When {\tt x} is {\tt 0}, it remains low until
    next active CB1 transition. When {\tt x} is {\tt 1}, CB2 remains low
    for one E cycle.\smallskip}} \\
& {\tt 110} & Reset CB2 \\
& {\tt 111} & Set CB2 \\ \hline

 2 & \multicolumn{2}{l|}{Register in address {\tt\$DFC2}} \\
& {\tt 0} & Data Direction Register \\
& {\tt 1} & Peripheral Register \\ \hline

 1 & \multicolumn{2}{l|}{Determine Active CB1 Transition} \\
& {\tt 0} & IRQB1 set by high-to-low transition on CB1 \\
& {\tt 1} & IRQB1 set by low-to-high transition on CB1 \\ \hline

 0 & \multicolumn{2}{l|}{CB1 Interrupt Request Enable/Disable} \\
& {\tt 0} & Disable \overbar{IRQB} Interrupt by CB1 active transition. \\
& {\tt 1} & Enable \overbar{IRQB} Interrupt by CB1 active transition. \\ \hline
\end{tabular}
\end{center}
\caption{The PIA address {\tt\$DFC3} ({\tt 57283})}
\label{DFC3}
\end{table}

\subsection{Programming the MMU}

In the Commodore~128 Programmer's Reference Guide, starting at page 530,
there is a list of the MMU registers. Apparently, the engineers at
Commodore planned to produce successors for the MOS~8722~MMU that is used
in the Commodore~128. There could have been at least two different chips:
one that could access 256 kilobytes of memory (just like my MMU
expansion), and another one for accessing a whole megabyte. The one
megabyte memory space could have been implemented with 256 kilobit chips,
whose MA8 line could have been produced in the MMU. Alternatively, they
could have used the smaller 4164 memory chips. 128 memory chips would
have taken quite a lot of printed circuit board space.

Commodore's plans for the one megabyte expansion were not so bright. Each
bank would have been expanded to 256 kilobytes, just like in the PIA
expansion, but you would have had to switch all 64 kilobytes on at once.
Well, maybe they were going to use the common memory scheme in that
expansion. Anyway, Commodore canned the plans for the new MMU's in a very
early phase and started to produce external DMA-based RAM Expansion
Units, REU's, which are supported also in the C128's operating system.

The Tables \ref{MMUregs} to \ref{MMU_SVR} describe the MMU registers.
Please ignore the `RAM block' setting of the RAM Configuration Register.
The System Version Register (Table \ref{MMU_SVR}) should always return
{\tt\$20} upon reading, so you have to use other techniques if you want
to determine the real amount of memory banks on the system. Actually, the
only difference between MMU expanded systems and unexpanded ones is that
the banks {\tt 2} and {\tt 3} map to banks {\tt 0} and {\tt 1} on stock
C128's.

The Configuration Register (Table \ref{MMU_CR}) reflects the memory
configuration state upon reading, and whenever you write to it, the new
memory configuration will be selected immediately. If you have selected
the I/O block at {\tt\$D000}, you can access the CR at {\tt\$D500}, but
the address {\tt\$FF00} is available in all memory configurations.
Generally, the processor addresses {\tt\$FF00}--{\tt\$FF04} are always
mapped to the MMU.

There are also Preconfiguration registers, which let you to change
configurations easier. If you write anything to a Load Configuration
Register, the value in the corresponding Preconfiguration Register will
be loaded to the Configuration Register, thus selecting that memory
configuration. Upon reading, the Load Configuration Registers reflect
the state of the corresponding Preconfiguration Register. These
registers are normally used by the BASIC interpreter, so if you want
your routines to coexist with the BASIC, it is probably best to leave
those registers alone.

The Mode Configuration Register (Table \ref{MMU_MCR}) lets you to change
processors and operating modes, among others. All bits in this register
act as outputs, but they can be used as inputs, too. If you wrote a
`{\tt 1}' to any bit, external hardware could pull the line down, and
the bit would output `{\tt 0}'. For instance, you can make the operating
system to think that the 40/80 key is depressed by clearing the high bit
of this register. Also, if you make your own routine to select the C64
mode, you will able to assert the \overbar{EXROM} or \overbar{GAME}, if
you want to play with different C64 mode memory configurations without
having to hook anything to the computer. Also, note that you can use
other banks than the default {\tt 0} in the C64 mode, if you disable
common memory and remember to select the video bank.

The 64~kB video bank can be selected with the RAM Configuration Register
(Table \ref{MMU_RCR}). Its other purpose is selecting the size and
location of the Common RAM block, a memory area that defaults to bank
{\tt 0} in spite of the processor RAM bank settings in the Configuration
Registers.

Finally, the page relocation registers let you to relocate the processor
pages zero and one (addresses {\tt\$00}--{\tt\$FF} and {\tt\$100}--%
{\tt\$1FF}) anywhere in the memory. Well, actually the 8502's addresses
{\tt 0} and {\tt 1} always map to its built-in I/O register. In addition
to that, the MMU defaults the page relocation bank to {\tt 0} if you are
using common memory at bottom of memory. To relocate the zero page,
first write the memory bank ({\tt 0}--{\tt 3}) to {\tt\$D508}, and then
write the memory page number to ({\tt\$D507}). The stack page (page
{\tt 1}) uses the addresses {\tt\$D509} and {\tt\$D50A}.

\begin{table}
\begin{center}
\begin{tabular}{|c|c|l|}
\hline
{\bf Address} & \multicolumn{2}{l|}{\bf Description} \\ \hline
{\tt\$D500} & CR   & Configuration Register \\
{\tt\$D501} & PCRA & Preconfiguration Register A \\
{\tt\$D502} & PCRB & Preconfiguration Register B \\
{\tt\$D503} & PCRC & Preconfiguration Register C \\
{\tt\$D504} & PCRD & Preconfiguration Register D \\
{\tt\$D505} & MCR  & Mode Configuration Register \\
{\tt\$D506} & RCR  & RAM Configuration Register \\
{\tt\$D507} & P0L  & Page 0 pointer low \\
{\tt\$D508} & P0H  & Page 0 pointer high \\
{\tt\$D509} & P1L  & Page 1 pointer low \\
{\tt\$D50A} & P1H  & Page 1 pointer high \\
{\tt\$D50B} & SVR  & System Version Register \\
\hline
{\tt\$FF00} & CR   & Configuration Register \\
{\tt\$FF01} & LCRA & Load Configuration Register A \\
{\tt\$FF02} & LCRB & Load Configuration Register B \\
{\tt\$FF03} & LCRC & Load Configuration Register C \\
{\tt\$FF04} & LCRD & Load Configuration Register D \\
\hline
\end{tabular}
\end{center}
\caption{The MOS 8722 MMU registers}
\label{MMUregs}
\end{table}

\begin{table}
\begin{center}
\begin{tabular}{|c|c l|}
\hline
\multicolumn{3}{|c|}{\bf Configuration Register format} \\
\hline
 Bit(s) & \multicolumn{2}{l|}{Description} \\ \hline
 7--6 & \multicolumn{2}{l|}{Processor RAM bank ({\tt 0}--{\tt 3})} \\
 5--4 & \multicolumn{2}{l|}{Contents of the area {\tt\$C000}--{\tt\$FFFF}} \\
      & {\tt 00} & Kernal ROM \\
      & {\tt 01} & Internal Function ROM \\
      & {\tt 10} & External Function ROM (\overbar{ROMH}) \\
      & {\tt 11} & RAM \\
 3--2 & \multicolumn{2}{l|}{Contents of the area {\tt\$8000}--{\tt\$BFFF}} \\
      & {\tt 00} & BASIC ROM high \\
      & {\tt 01} & Internal Function ROM \\
      & {\tt 10} & External Function ROM (\overbar{ROML}) \\
      & {\tt 11} & RAM \\
 1    & \multicolumn{2}{l|}{Contents of the area {\tt\$4000}--{\tt\$7FFF}} \\
      & {\tt 0}  & BASIC ROM low \\
      & {\tt 1}  & RAM \\
 0    & \multicolumn{2}{l|}{Contents of the area {\tt\$D000}--{\tt\$DFFF}} \\
      & {\tt 0}  & I/O registers \\
      & {\tt 1}  & RAM or character generator ROM \\
\hline
\end{tabular}
\end{center}
\caption{The MOS~8722~MMU Configuration Registers
({\tt\$D500}--{\tt\$D504} and {\tt\$FF00}--{\tt\$FF04})}
\label{MMU_CR}
\end{table}

\begin{table}
\begin{center}
\begin{tabular}{|c|c l|}
\hline
\multicolumn{3}{|c|}{\bf Mode Configuration Register} \\
\hline
 Bit(s) & \multicolumn{2}{l|}{Description} \\ \hline
 7    & \multicolumn{2}{l|}{40/80 key sense} \\
 6    & \multicolumn{2}{l|}{Operation mode selection} \\
      & {\tt 0} & C128 \\
      & {\tt 1} & C64 \\
 5    & \multicolumn{2}{l|}{\overbar{EXROM} line control} \\
 4    & \multicolumn{2}{l|}{\overbar{GAME} line control} \\
 3    & \multicolumn{2}{l|}{Fast Serial bus direction} \\
 2--1 & \multicolumn{2}{l|}{unused} \\
 0    & \multicolumn{2}{l|}{Processor selection} \\
      & {\tt 0} & Z80 \\
      & {\tt 1} & 8502 \\
\hline
\end{tabular}
\end{center}
\caption{The MOS~8722~MMU Mode Configuration Register ({\tt\$D505})}
\label{MMU_MCR}
\end{table}

\begin{table}
\begin{center}
\begin{tabular}{|c|c l|}
\hline
\multicolumn{3}{|c|}{\bf RAM Configuration Register} \\
\hline
 Bits & \multicolumn{2}{l|}{Function} \\ \hline
 7--6 & \multicolumn{2}{l|}{Video RAM bank ({\tt 0}--{\tt 3})} \\
 5--4 & \multicolumn{2}{l|}{RAM block ({\tt 0}--{\tt 3})} \\
 3--2 & \multicolumn{2}{l|}{Common RAM selection} \\
      & {\tt 00} & Common RAM block disabled \\
      & {\tt 01} & Common RAM block at bottom of memory \\
      & {\tt 10} & Common RAM block at top of memory \\
      & {\tt 11} & Common RAM block at both top and bottom \\
 1--0 & \multicolumn{2}{l|}{Size of Common RAM block} \\
      & {\tt 00} & 1~kB \\
      & {\tt 01} & 4~kB \\
      & {\tt 10} & 8~kB \\
      & {\tt 11} & 16~kB \\
\hline
\end{tabular}
\end{center}
\caption{The MOS~8722~MMU RAM Configuration Register ({\tt\$D506})}
\label{MMU_RCR}
\end{table}

\begin{table}
\begin{center}
\begin{tabular}{|c|l|}
\hline
\multicolumn{2}{|c|}{\bf System Version Register} \\
\hline
 Bits & Description \\ \hline
 7--4 & Bank version (amount of 64~kB banks) \\
 3--0 & MMU chip version \\
\hline
\end{tabular}
\end{center}
\caption{The MOS 8722 MMU System Version Register ({\tt\$D50B})}
\label{MMU_SVR}
\end{table}

\subsection{Hints for programming in C128 mode Machine Language}

It is best to use sixteen or thirty-two kilobytes of common memory on
the MMU when using the PIA expansion. This way you can hold your program
in bank {\tt 0} in the lowmost or highmost sixteen kilobytes, or both,
and you can easily access all of the memory through two 16-kilobyte
windows at {\tt\$4000} and {\tt\$8000}. However, keep in mind that the
page relocation cannot be used outside bank {\tt 0} when the low common
memory block has been selected.

If you are working with graphics, switch the character generator ROM
off, and you have one restriction less. The three lowmost bits of the
processor's built-in I/O register (at addresses {\tt 0} and {\tt 1})
have totally different function in the C128 mode. The lowmost bit,
LORAM, selects one of the two color memory banks for the processor. The
second bit from right, \overbar{HIRAM}, selects the color memory bank
for the video chip. The CHAREN bit, bit~{\tt 2}, dictates whether the
character generator ROM is mapped to the video chip addresses
{\tt\$1000}--{\tt\$1FFF} or not.

\subsection{Programming in C128 mode BASIC}

Due to the complexity of the C128's operating system, it is very
difficult, if not impossible, to utilize the PIA expansion memory in
BASIC 7.0. You have to leave the segments {\tt 0} and {\tt 3} alone, as
they contain system variables, routines to access different RAM banks,
and interrupt vectors. The other segments are not safe either, as the
BASIC interpreter uses all of the RAM bank {\tt 1} for BASIC
variables. If you switch other RAM blocks to a segment, you will have to
ensure that no BASIC program data or variables occupy any of the address
range used by that segment.

For this reason, I did not even try to find out how you could utilize
the PIA expansion in the BASIC 7.0. But you can use the MMU expansion
RAM very easily with the built-in {\tt BANK} command. The new RAM banks
have the numbers {\tt 2} and {\tt 3}.

If you really want to utilize the PIA expanded memory in BASIC 7.0
programs, it is possible by using machine language subroutines to access
the extra memory. Remember to disable the interrupts in your subroutine,
as the BASIC interpreter uses raster interrupts.

\section{Programming the expansion in C64 mode BASIC}

With BASIC 2.0 the use of the extra memory is a bit limited. In the
upmost segment (segment~{\tt 3}) there is operating system ROM, under
which you can place different memory blocks, but reading them with BASIC
is naturally impossible. However, in some cases writing data to this
segment partially under Kernal~ROM and I/O area may be a working
solution. The lowmost kilobytes are free RAM, and it can be utilized by
switching memory blocks. But the benefit of the extra memory decreases,
as you can use only the lowmost four kilobytes of each block.%
\footnote
{
  You can read and write the area {\tt\$C000}--{\tt\$DFFF} of this
  segment using BASIC. Accessing the area {\tt\$D000}--{\tt\$DFFF} 
  without machine language is tricky but possible.
}

The highest segment but one, segment~{\tt 2}, is halfly under BASIC ROM,
and only its lower half can be freely used.%
\footnote
{
  You can always write under ROM (except in the UltiMax game cartridge
  configuration).
}
When utilizing it, you have to take in consideration that those 8
kilobytes can be under a ROM module, if one is connected, or they could
hold some of the variables and tables that are stored in the top of the
BASIC memory. You have to construct your programs so that they do not
collide with the segment's area.

The lowmost segment, segment~{\tt 0}, contains Kernal's and BASIC
interpreter's system variables. Normally you cannot change its contents,
since the operating system would not find its status information. This
can be worked around by copying those vital bytes to the new memory block
and switching the block with a machine language routine.

The only segment that can be wholly used with plain BASIC is the
segment~{\tt 1}, the second one from the bottom ({\tt\$4000}--%
{\tt\$7FFF}). It resides in the middle of the space reserved for BASIC
programs. If you construct your BASIC programs wisely, that is short
enough, and ensure that the information used by BASIC are located
exactly on this area, you can switch the blocks in this segment freely
and exploit all the twelwe extra blocks as a huge data storage.

Example~\ref{BigArray} shows how you can create a table on this area
and hold its data simultaneously in all the extra memory blocks.

\subsection{Processing a huge array}

\label{BigArray}
\begin{quote}
\begin{verbatim}
10 I=0:J=0:K=0:A=0
20 DD=56576:PIA=57280
30 FOR I=11 TO 0 STEP -1:READ A:POKE PIA,A:NEXT
31 DATA 4,254,4,220,0,255,0,255,4,254,52,220
40 K=16384-7:POKE 47,K AND 255:POKE 48,K/256:
   POKE 49,K AND 255:POKE 50,K/256
50 DIM A%(8191)
60 FOR I=0 TO 15:POKE PIA,I*16+12
70 PRINT I":";:FOR J=0 TO 9:PRINT A%(J),:NEXT:PRINT:NEXT
80 POKE PIA,220:END
\end{verbatim}
\end{quote}

The program displays ten first integers of each memory block. The table
it reserves fills the whole segment~{\tt 1}, because each integer
(notice the {\tt\%} sign) takes two bytes and 8192 of them are reserved.
The contents of the table {\tt A\%} can be changed to another memory
block by simply {\tt POKE}ing PIA's corresponding register. On the line
{\tt 40} the table is ensured to start at {\tt\$4000} by changing the
start and end addresses of tables in the addresses {\tt 47}--{\tt 50}.
Saving the name, size and dimensions of the table takes the seven bytes,
which are subtracted from the start address.

Reserving the table to an arbitrary address has its drawbacks. The size
of the program and its variables may not exceed 14 kilobytes so that
they could fit to the memory before the beginning of the table. All
variables must definitely be declared before allocating the table. If
you do not declare them by giving them a value, the interpreter finds
really exotic values for them or transfers the table off its position.

\subsection{Storing graphics}

\begin{quote}
\begin{verbatim}
10 I=0:J=0:A=0:A$=""
20 DD=56576:PIA=57280:V=53248:COLOUR=50176
30 FOR I=11 TO 0 STEP -1:READ A:POKE PIA,A:NEXT
31 DATA 4,254,4,220,0,255,0,255,4,254,52,220
40 POKE V+24,16+8:POKE V+17,59
50 FOR I=0 TO 11:POKE PIA+2,I*16+14:
   POKE DD,PEEK(DD) AND 252 OR (NOT I AND 3)
60 FOR J=0 TO 999:POKE J+COLOUR,3:NEXT
70 GET A$:IF A$="" THEN 70
80 NEXT I
90 POKE PIA+2,254:POKE DD,PEEK(DD) OR 3:
   POKE V+24,23:POKE V+17,27
\end{verbatim}
\end{quote}

The extra memory can be used as a store of high resolution pictures as
well. This program shows all twelve memory areas that could contain
reasonable pictures. The pictures can be created with a BASIC extension
that resides in RAM and saves its graphics under Kernal ROM. In those
memory blocks that contain no pictures, you see random memory contents.

High resolution graphics is enabled on the line {\tt 40}. The beginning
of the line {\tt 50} switches block {\tt I} to the segment~{\tt 3} and
switches the VIC chip to the same memory area. The second {\tt POKE}
statement selects the block for the video chip. `{\tt (NOT I AND 3)}'
filters the extra bits off and inverts the essential ones so that they
can be stored to the lowmost two bits of {\tt\$DD00}. The line {\tt 60}
sets the picture's colour to black-cyan. The next line waits for a
keystroke before showing another picture. After all blocks have been
shown, the original state of the I/O chips will be restored on the line
{\tt 90}.

\section{RAM disk and other C64 mode programs}

As memory expansions are expensive, programs making use of extra memory
are rare. Besides, different expansions are not compatible with each
other. However, it does not mean that you could not fully utilize the
expansion. The most obvious utilization method is a RAM disk. When using
VC-1541, it is not only luxury but almost vital condition.

Pekka Pessi has made a couple of C64 programs that utilize the PIA
expansion. The software is distributed in two self-extracting archive
files ({\tt SFX}es).%
\footnote
{
  If you haven't got the files with this document, you can retrieve
  them via anonymous FTP from {\tt FTP.FUNET.FI}. The directory
  {\tt /pub/cbm/documents/projects/memory/c128/1028} contains files
  related to this expansion.
}

The file {\tt ROS-V1.SFX} (for RAM Operating System) holds the source
code of the RAM disk program, and some miscellanous files. To load the
archive file, use the command ``{\tt LOAD"ROS-V1.SFX",}{\it device\/}''.
Then change a blank disk to the drive before {\tt RUN}ning. The second
archive file, {\tt UTIL256.SFX}, contains the following software:

\subsection{Memory test}
\label{TEST}

The program {\tt TEST} tests the block selection and the whole memory.
If it jams before reporting ``{\tt Test passed}'', something has gone
wrong. Its source code is in the file {\tt TEST.A}, which requires a
library {\tt STRING.A}. I translated the executable to English by
patching the binary file.

\subsection{Poor man's multitasking}
\label{MULTI51200}

With the {\tt MULTI51200} program you can run four different programs.
The program does no multitasking, it only holds four environments in the
memory, each in its own memory block. {\tt MULTI.A} is the source code.
After loading it with ``{\tt LOAD"MULTI51200",{\it device},1}'' and
initializing the BASIC pointers with ``{\tt NEW}'', you can switch the
environments with ``{\tt SYS51200,{\it f},{\it b\/}}''. The parameter
{\it f\/} is a flag determining if the current block should be copied to
the destination block ({\tt 0}) or not ({\tt 1}). The {\it b} selects
the destination block ({\tt 0}--{\tt 3}). The initial block is {\tt 3}.

\subsection{Machine language monitor}

If you don't like to switch the memory blocks manually in your favourite
machine language monitor, the {\tt MON256} utility is for you. The memory
is again divided to four 64~kB blocks, numbered from 0 to 3. The commands
are explained in Table~\ref{MON256}.

\begin{table}
\begin{center}
\begin{tabular}{|l|l|}
\hline
{\parbox{1.6in}{\smallskip 
{\tt a \it nnnn cmd\/} or \\ {\tt .\ \it nnnn cmd}\smallskip}} &
{\parbox{2.8in}{\smallskip
Assembles instruction {\it cmd\/} to memory address {\it nnnn}.\smallskip}}
\\\hline
{\tt b \it bb ff} &
{\parbox{2.8in}{\smallskip Selects a block. The {\it bb\/} holds the
block number, and {\it ff\/} is a flag. If it is {\tt 1}, it directs all
memory accessing to RAM. If it is {\tt 0}, you can access the ROMs and
I/O.\smallskip}}
\\\hline
{\tt c \it hhhh iiii jjjj} &
{\parbox{2.8in}{\smallskip Compares the memory area {\it hhhh}--{\it iiii\/}
with the area beginning from {\it jjjj}.\smallskip}}
\\\hline
{{\tt d} [{\it hhhh\/} [{\it iiii\/}]]} & {\parbox{2.8in}{\smallskip 
Disassembles memory.\smallskip}}
\\\hline
{\tt f \it hhhh iiii nn} &
{\parbox{2.8in}{\smallskip Fills the memory between {\it hhhh\/} and
{\it iiii\/} with the byte pattern {\it nn}.\smallskip}}
\\\hline
{{\tt g} [{\it hhhh\/}]} &
{\parbox{2.8in}{\smallskip Executes program until a {\tt BRK} 
is encountered.\smallskip}}
\\\hline
{\parbox{1.6in}{\smallskip{\tt h \it hhhh iiii nn mm\ldots} or \\
{\tt h {\it hhhh iiii\/} '{\it text}}\smallskip}} &
{\parbox{2.8in}{\smallskip Hunts the memory area {\it hhhh}--{\it iiii\/}
for the byte sequence {\it nn mm\ldots} or for {\it text}.\smallskip}}
\\\hline
{{\tt j} [{\it hhhh\/}]} & {\parbox{2.8in}{\smallskip 
Calls a subroutine.\smallskip}}
\\\hline
{{\tt l "{\it filename\/}"}[{\tt ,}{\it n\/}]} &
{\parbox{2.8in}{\smallskip Loads a program.
Default device number is 8.\smallskip}}
\\\hline
{{\tt m} [{\it hhhh\/} [{\it iiii\/}]]} & {\parbox{2.8in}{\smallskip
Hexadecimal dump of memory.\smallskip}}
\\\hline
{\tt >\it hhhh nn mm\ldots} & {\parbox{2.8in}{\smallskip
Stores bytes in memory.\smallskip}}
\\\hline
{\tt r} & {\parbox{2.8in}{\smallskip Dumps the registers 
(for {\tt g} and {\tt j}).\smallskip}}
\\\hline
{\tt ;} & {\parbox{2.8in}{\smallskip Modifies the register values.\smallskip}}
\\\hline
{\tt s "{\it filename\/}",{\it n},{\it hhhh},{\it jjjj}} &
{\parbox{2.8in}{\smallskip
Saves the memory area {\it hhhh}--{\it jjjj}.\smallskip}}
\\\hline
{\tt t \it hhhh iiii jjjj} & 
{\parbox{2.8in}{\smallskip Copies the memory area {\it hhhh}--{\it iiii\/} to
{\it jjjj}.\smallskip}}
\\\hline
{{\tt v "{\it filename\/}"}[{\tt ,}{\it n\/}]} & {\parbox{2.8in}{\smallskip
Verifies a program. Default device number is 8.\smallskip}}
\\\hline
{\tt x} & {\parbox{2.8in}{\smallskip Exits the monitor.\smallskip}}
\\\hline
{{\tt \verb|@|} [{\it command\/}]} &
{\parbox{2.8in}{\smallskip Sends {\it command\/} to device~8. If it
begins with {\tt\$}, the disk directory will be read. If no command
is given, the disk drive's status will be displayed.\smallskip}}
\\\hline
\end{tabular}
\end{center}
\caption{Commands for the {\tt MON256} utility}
\label{MON256}
\end{table}

The source code for the monitor is split in the files {\tt MON.A}, 
{\tt CONSOLE.A}, {\tt COM.A}, {\tt ROUTINES.A} and {\tt TABELS.A}.

\subsection{RAM disk}
\label{RAMdisk}

The most important utility is a RAM disk program, which occupies about 9
kilobytes of memory. It transfers Kernal and BASIC interpreter to RAM
and patches the serial bus routines. The actual program is in the area
{\tt\$00800}--{\tt\$03FFF}.

It emulates all VC-1541 functions except relative files. For example,
the commands {\tt U1}, {\tt U2}, {\tt B-A} etc. work. {\tt UI+} and {\tt
UI-} make no difference. The program also detects some fast loaders and
works with them installed.

The loader is called {\tt RAM DISC}, and the patched Kernal is in {\tt
RAM.K}. You need only patches to the low-level serial bus routines, so
you may want to restore the original colors and keyboard definitions. To
minimize incompatibility problems, you should replace the ROM chip that
holds the BASIC and Kernal ROMs with an EPROM containing the patched
Kernal. The RAM disk routines are in {\tt RAM.C}.

\subsubsection{Disk copiers}

The program {\tt RAM DISC COPY} copies a regular 1541 disk to RAM. It
utilizes the slow {\tt U1} command, and it is included as an example
only. The source code {\tt DUP.A} exposes the RAM disk's storage format.

A faster and more useful tool is {\tt FDUPLICATE}. Using it, you can
copy a regular disk to the RAM disk or vice versa. You can make multiple
copies of a disk easily. This program's fast transfer routines are
designed for PAL systems, and the utility cannot be used in NTSC
machines without little modification. Its source code is in the two
files {\tt S/SUCK} and {\tt S/DSUCK}.

\section{Enhancing the PIA expansion} 
\label{Expanding}

There are a couple of unused contacts in the PIA. In addition to that,
two 7405 ports are not connected. The extra PIA lines include an input,
CB1, an input/output line CB2, and the Interrupt Request line
\overbar{IRQB}.

If you connect the \overbar{IRQB} line to the \overbar{IRQ} or
\overbar{NMI} input of your system, you can have one or two new interrupt
sources, useful for interfacing your custom hardware. And if you are
running out of User Port pins, the lines CB1 and CB2 can save you from
designing an I/O cartridge. Besides, you can use the \overbar{IRQB} as an
output if you wire the CB1 line to something that you can control with
software, CA2 for instance. Just remember to add a pull-up resistor to
the \overbar{IRQB} line if necessary.

\subsection{Built-in freezer}
\label{Freezer}

For the Commodore 64, there are several `freezer' cartridges that let the
user to halt theoretically any program (game) to alter it (make the
player immortal), or more often merely to make a `back-up copy' of it.
Alas, anything cannot be frozen with these cartridges. If the programmer
of the game is clever enough to inhibit IRQ and NMI interrupts in his
program, and if the code runs at the area {\tt\$0000}--{\tt\$0FFF}, no
external cartridge will be able to halt it without asserting the
\overbar{RESET} signal, which would lose most status information of the
computer.

You can use the PIA expansion to freeze programs, in many cases also in
the C128 mode. In the C64 mode, an internal freezer can stop anything
except a totally jammed program. In the C128 mode, it can stop software
running on the 8502 without using any ROM at the area
{\tt\$C000}--{\tt\$FFFF}.

This freezer expansion will let you to replace the program's memory with
previously initialized RAM by pressing the Restore key. If the NMI
interrupts are disabled, freezing will be done with the BRK instruction.
As the circuit forces the \overbar{HIRAM} line to logical zero, the C64
mode interrupt vectors will always be fetched from RAM. All of the
freezer software can be stored to RAM, so it is easy to change, and no
EPROM programming devices are needed. Another advantage is that the
freezer software may freely use 128 kilobytes of memory, and there are
64 kilobytes of working storage, way more than in the best freezer
cartridges. Besides, those amounts will be at least doubled or
quadrupled in the C128 mode freezer, depending on whether you have built
the MMU expansion.

For this expansion, you need a double ON--OFF or ON--ON switch, four
1N4148 diodes and two $\rm 10~k\Omega$ resistors. First do some
preparations. Break the connection between the PIA's \overbar{RESET}
input (pin~34) and the system \overbar{RESET}, and replace it with a
diode with the marked end towards the system bus, so that the pass
direction is from the PIA to the system \overbar{RESET}. Then you have to
solder a pull-up resistor between the PIA's \overbar{RESET} line and the
+5~V power outlet. Locate the U29 chip (7406) on the motherboard and
desolder its pin~4. Solder a diode between the motherboard connection and
the pin with the mark pointing to the chip. Finally, solder the other
pull-up resistor between the U29's pin 4 and +5~V. After these
modifications, the PIA should continue to reset normally, and the Restore
key should remain functional.

Now you can mount the switch to the system. If you have an ON--ON switch,
hold it in your hand in such an angle that you see two rows of three
pins. Solder two diodes from the right-hand contacts of the switch to the
U29's pin~4, with the mark pointing to the U29. Solder the PIA's
\overbar{RESET} line (pin~34) to either middle contact of the switch, or
to either free contact if you have an ON--OFF switch. Finally, mount the
\overbar{HIRAM} line, which is on the 8502's pin~29, to the remaining
middle contact.

The switch affects in the operation of the Restore key. When it is open,
the Restore key operates normally. When the switch is closed, the Restore
key also resets the PIA, switching the default memory blocks in, and
forces the \overbar{HIRAM} line low, so that the interrupt vectors will
always be fetched from RAM. The idea of the expansion is that the program
runs in some other memory blocks, say {\tt 3}--{\tt 0}, with the PIA
totally disabled from the address space. The default memory blocks
({\tt\$F}--{\tt\$C}) will be initialized mostly with null bytes, which is
the opcode of the {\tt BRK} instruction. You also need the freezer interrupt
vectors ({\tt\$FFFA}--{\tt\$FFFF}) and a small interrupt handler that
stores the processor registers and switches the main freezer program into
the address space.

If you want to freeze hanged programs, too, you can do it without losing
the state of the I/O chips. By using a custom Kernal ROM, you could even
store all 8502 registers except the Program Counter. You just have to be
able to reset the 8502 without resetting the rest of the chips. To do
this, desolder the \overbar{RESET} signal, pin~40 on the 8502. Connect a
1N4148 diode between the system \overbar{RESET} signal and the 8502, with
the mark pointing away from the processor. Add a pull-up resistor to the
signal, and a switch between the logical ground and the signal.

Now, whenever you push the switch, only the 8502 will be reset. If the
computer is in the C64 mode at this time, it will remain in that mode,
since the MMU does not get reset. You should then use the Autostart code
({\tt\$C3 \$C2 \$CD \$38 \$30} at {\tt\$8004}--{\tt\$8008}), and the
Kernal will jump to the vector {\tt(\$8000)}. Unfortunately it will
destroy all registers except the {\tt Y} register when searching for that
code. More fortunately, if the computer is in the C128 mode, and if the
Kernal ROM is not selected in the memory configuration, the processor
will fetch the \overbar{RESET} vector from the active RAM bank. In that
case you can store all processor registers except the program counter.

Alas, I just have invented a software hack that cannot be frozen with
this circuit. If a program runs on the I/O area ({\tt\$DE00}--{\tt\$DFFF}
except the range where the PIA is mapped to while the I/O is switched on)
and has disabled the NMI interrupts, the program will continue running
even if you have activated the freezer and hit the Restore key. Should
you ever encounter this type of a software hack, you can use a triple
switch and add the \overbar{LORAM} signal (8502's pin~30) to one extra
contact. Connect the remaining contact to the U29's pin~4 through a diode
with the mark pointing to the U29. This will disable the I/O area for the
time the Restore signal is active, so the processor can fetch a {\tt BRK}
from the memory underneath, and will always freeze correctly.

I haven't completed the freezer expansion yet, as the daughter-board in
my faithful 2564 (C64 with the 256~kB expansion) stopped working when I
opened the cover to start the surgery operation. My first attempt of
rebuilding it did not succeed, and now I am in Germany, more than one
megameter away from the computer. When returning to Finland in August
1994, the freezer expansion will be one of my first projects I am going
to finish.%
\footnote
{
  So I thought at that time---as of December 1999, I have neither
  fixed that particular C64 nor completed the freezer expansion.
  Besides, the expansion would not have much advantage over freezer
  cartridges or the features present in some emulators.
}

Naturally you also need a program to utilize the freezer circuitry. You
don't need to code so much, only the routine to jump back to the freezed
program and the routine that saves all registers upon freezing need to be
written from scratch. You can patch existing machine language monitors,
sprite editors and utilities like that, only the data fetch and data
store subroutines must be rewritten. Developing the freezer software is
very simple, since you can access the frozen program through a 16~kB
window, and you can use the Kernal routines all the time.

\subsection{New operating system}

In my C64, I have replaced the 2364 Kernal ROM with a 32-kilobyte EPROM.
The two extra address lines are controlled by the PIA's pins CA2 and
CB2. As the C128 uses a 23128 ROM for both C64 BASIC ROM and Kernal ROM,
this type of expansion cannot be used. Besides, you can access only 256
kilobytes of the memory in the C64 mode. Why would you want to improve
the C64 mode if you can make the C128 mode far better?

The C128 has a socket for a Function ROM for your operating system
extensions. It can hold a 27256 EPROM, 32 kilobytes. If that does not
satisfy your needs, you could use a 27512 EPROM instead. In this case
you have to bend the A15 line up. This line could be controlled by the
PIA's CB2 line. To ensure that the logic works also when the CB2 line is
input, add a $4.7~{\rm k\Omega}$ pull-up resistor between CB2 and +5~V.

\section{Contacting the author}

If you have anything to ask or comment, feel free to contact me. If
you complete either or both expansions, I would like to have an E-mail
message or a postcard from you, so that I know I didn't write this
document in vain. Finally, if you make any software for the expansion
or patch existing programs to make use of the extra memory, I would
love to put the software available on the FTP site {\tt FTP.FUNET.FI}.

My addresses are:

\begin{tabular}{r l}
\\ {\em InterNet:} & {\tt Marko.Makela@FTP.FUNET.FI}
\\ {\em Mail:}
  & Marko M\"akel\"a
\\& Harakankuja 6 D 19
\\& FIN-02600 Espoo
\\& Finland
\end{tabular}

\end{document}
