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Scope on the C64

Content

Introduction

Supply Voltages

RESET

Clock Signals

AEC (Address Enable Control)

DRAM Refresh

Data Bus

Address Bus

Chip Selects

Video Signals

The Interrupts

Intoduction

If all diagnostic instruments fail on a C64 repair, there is some "more advanced" instrument, that helps one to debug a faulty C64: the scope.

Sure, not everybody has one. But in case you have a scope, you still need to have a reference showing the good case. And that is, what this essay is all about.

You should understand the scape basics already, being able to set the coupling, the trigger (source and edge), the time base and the voltage per division on each channel. A dual channel scope with 20MHz or better 50MHz) is sufficient. The measurments here were conducted with a Rigol MSO4024 (upgraded to 350MHz bandwidth).

The GND clamp of the probe is connected to the GND "frame" arund the board. I have soldered so pins to it.

The status is bootet up, no program execution.

THIS IS A WORK IN PROGRESS!

Supply Voltages
There are sure more exciting signals than the supply voltages in a C64. But in case they are bad, everything is bad, so it is well worth inspecting them.

The +5VDC are probed on Pin 6 of the CPU (U6).

The settings:
Coupling = DC
Time = 100µs/DIV
Voltage = 2V/DIV

ASSY 250469, 5VDC, DC coupling

This shows, that the curve is flat (at about 5V). If not, this is critical for the function and might show a malfunction of the PSU.

There is some ripple on the 5VDC, though. The power supply (in case it is a modern one and not the original) introduces maybe 100mV or 200mV (peak-peak), which is not critical or harmfull. Also, there is quite something going on in the C64, which causes further ripple.

The settings:
Coupling = AC
Time = 100µs/DIV
Voltage = 200mV/DIV

ASSY 250469, Ripple on 5VDC (AC coupling)

In ASSY 250469, there is the +9/12V, which is supplying the SID (U9 at Pin 28). This is generated from the 9VAC from the power supply.

Again, this should be smooth with a small ripple.

The settings:
Coupling = DC
Time = 1µs/DIV
Voltage = 2V/DIV

ASSY 250469, +9/12V (DC coupling)

Settings:
Coupling =AC
Time = 1µs/DIV
Voltage = 100mV/DIV

ASSY250469, +9/12V, Ripple

Again, the ripple is maybe 200mVpp.

RESET
The /RESET signal is absolutely essemntial for the C64 to boot properly. If this is not present, the computer will most probably not work. It can be found on the CPU (U6, Pin 40).

It has to stay LOW (=close to 0V) for a couple of 100ms after switching on the power and then go HIGH.

Settings:
Coupling = DC
Time = 50ms/DIV
Voltage = 2V/DIV

ASSY250469, /RESET signal (the 2nd (blue) channel +5VDC)

It is not really required to probe the 2nd channel, I have only done this to show the power up.

The duration of the (LOW) /RESET pulse is not very accurate, because it is generated by an R/C. For ASSY250469, U23 (a 74LS14) and some passive components (on is a 220uF e-cap) do the job. For earlier ASSYs, it id done by a 556 timer (U20).

Clock Signals
The clock signals synchronize everything in a coputer system. The are curical for the function. Besides the chrystal generator, the VIC-II is generating the PHI0 clock from the clocks provided by the chrystal generator.

Be aware, that the clock frequencies are (slightly) different for PAL and NTSC C64s.

The dot clock was probed at the VIC-II (U7, Pin 22). It is generated in teh christal generator (ASSY 250469: U20).
Settings:
Coupling = DC
Trigger= rising edge
Time = 50ns/DIV
Voltage = 2V/DIV

PAL ASSY 250469, Dot Clock (PAL: 7.463MHz, NTSC: 8.1818MHz)

The color clock was probed at the VIC-II (U7, Pin 21). It is generated in the christal generator (ASSY 250469: U20).

Settings:
Coupling = DC
Trigger= rising edge
Time = 20ns/DIV
Voltage = 2V/DIV

PAL ASSY 250469, Color Clock (PAL:17.73MHz, NTSC: 14.31818MHz)

PHI0 is the processor clock, which is generated by the VIC-II. It is probed at the CPU (U6, Pin 1).
Settings:
Coupling = DC
Trigger= rising edge
Time = 200ns/DIV
Voltage = 2V/DIV

PAL ASSY250469, Phi0 (984.2kHz for PAL, NTSC: )

PHI2 is the processor clock, which is generated by the CPU. It is probed at the CPU (U6, Pin 39).
Settings:
Coupling = DC
Trigger= rising edge
Time = 200ns/DIV
Voltage = 2V/DIV

PAL ASSY250469, Pih2 (PAL: 984.2kHz, NTSC: )

AEC: Address Enable Control
The AEC signal is generated by the VIC-2 chip. It determins, wether the VIC or the CPU might accress the system busses. This is another important signal, that is required for a working C64 (sure, everything is required, but this signal is a show stopper).

While AEC is HIGH, the CPU can access the RAM, while it is LOW, the VIC-2 acresses the RAM (e.g. for refreshing the DRAM). It also controls, who can access the color RAM.

The AEC signal can be probed in several locations, here it was U3, Pin4.

Settings:
Coupling = DC
Trigger= rising edge
Time = 500ns/DIV
Voltage = 2V/DIV

ASSY 250469 (PAL) - AEC

DRAM Refresh Signals
The VIC-2 refreshes the content of the DRAM periodically. A DRAM cell (bit) is actually a small capacitor, that holds the information (0 or 1). This capacitor has to be recharged after a short time, so it can keep the information).

The signals are probled at the 4x46k DRAMs of ASSY250469. RAS is Pin 5, CAS is Pin 16 of U10 and U11.

Settings:
Coupling = DC
Trigger= rising edge
Time = 500ns/DIV
Voltage = 2V/DIV

ASSY 250469: CAS (yellow) and RAS (blue)

Data Bus
The Data Bus is the highway, on whish the information is being transported from tze CPU to the RAM, the ROM and other peripherals and back. There is always activity on every bit of the data bus. It is not a steady display, but it is pretty random. Since the sources of data are different (data might be issued by teh CPU or might be read from one of the various peripherals), the levels are slightly different. Nevertheless, the LOW and the HIGH levels should not exceed or fall below certain levels. A 2V level is bad. A 3.5V to 5V level is still good.

The data bus can be probed at the CPU (U6, D[0..7] is Pin 37...30).

Settings:
Coupling = DC
Trigger= rising edge
Time = 500ns/DIV
Voltage = 2V/DIV

ASSY250469: Data Bus D0

D0 is representing all other data bus lines.

Address Bus
The Address Bus signals are issued by the CPU (A0...15) and the VIC-II (MA0...7). Both chips control the busses at certain times. The big PLA of ASSY250469 also accessed MA0..7, on earlier ASSYs, this job is also done by multiplexers (U13 and U25).

The Bits A0..15 can be probed at the CPU (U6, Pin 7...20, 22...23).

Settings:
Coupling = DC
Trigger= rising edge
Time = 500ns/DIV
Voltage = 2V/DIV

ASSY250469: Address Bit A0

ASSY250469: Address Bit A15

The lower address bits rather look like A0, the higher are a bit less active and look like A15. Both is ok.

The MA0-7 (multiplexed) address bits are used to access the DRAM. They can be measured there. On the ASSY250469 4x64k DRAM, they can be loacted on U10 and U11.

ASSY250469: MA0

Again, the display is not steady, but the levels should not be tied to one level only and the should be clearly LOW or HIGH (this can vary a bit, 4V are ok, 2V are not ok).

Chip Select Signals
The CPU issues the absolute address of the chip, that it wants to access, those chips do not have an inherent address, though. They know, that "they are meant" by a chip select signals, that solely addresses them. The chip, that translates the addresses to the chip selects is the PLA. The chip selects are "active low", which means, that it is HIGH while being inactive (most of the time) and go LOW, when the particular chip is addressed.

In case the address bus seems to be working (see the previous chapter), but the chips are not addressed, the PLA might be the culprit (or a dead chip, that ties the signals to a certain level).

Some of the chip selects are issued all the time, when the boot screen is displayed. The BASIC and Kernal (ASSY250469: U4) are then permanently accessed. The chip select is at pin 22. In earlier ASSYs, BASIC and Kernal are on different chips (U3 and U4). These chip selects can be found on pin 20 (each).

Settings (for all Chip Selects):
Coupling = DC
Trigger= rising edge
Time = 500ns/DIV
Voltage = 2V/DIV

ASSY 250469: Chip select U4 (BASIC & Kernal ROM)

The character ROM (U5) is pernanently accessed by the VIC-22. The chip select is located at Pin 20.

ASSY 250469: Chip select U5 (Character ROM)

There is also a permanent activity on U1, this CIA is responsible for the keyboard (scan). The chip select is on Pin 23.

ASSY 250469 Chip select U1 (CIA1 Keyboard scan)

The last chip with permanent activity is U19, the color RAM, which is permanently accessed by the VIC-II.CS is on Pin 8.

ASSY 250469: Chip select U19 (color RAM)

The chip selects of the other peripherals, like CIA2 (U2, Pin 23), SID (U9, Pin 8) and VIC (U7, Pin 10) are inactive, while the C64 is ideling on the boot screen. They require a certain software to be active. A Diagnostic Rev. 586220 will access those chips, while they are tested (most of the time, they are still not tested). Setting the scope to "single shot" will be able to detect such a CS-pulse. You need to be patient for that. The result will probably look like the CS of U1.

The Video Signals
In case there is no video being displayed on your monitor, it might be useful to check the output of the VIC-II and the RF modulator to exclude a broken video cable or a not working display.

The settings for the video signals are:
Coupling = DC
Trigger= rising edge
Time = 10us/DIV
Voltage = 500mV/DIV

Please keep in mind:
1. The video signals are analog signals (no LOW and HIGH levels here)
2. The signals depend on the content of the display. Other colors (other kernals) might have different signal forms. This is teh regulat boot screen in light blue/blue.
3. It is not very easy to get a steady signal here. it might require fiddling with the trigger level.

The SLUM signal is generated on the VIC-II. It can be found at U7, Pin 15. It is the LUMA signal, before the processing in the RF-modulator. The RF-Modulator does have an influence on the signal, even if no TV (RF) output is required.

The SLUM signal of the VIC-II for light blue border and blue background

Here, every of those "cycles" and a scan line on the display. First comes the Hsync pulse, then come the boarder (brighter than the background), the the background (the voltage is lower). the scann lines on top and bottom of the screen are light blue. This is, why there is a 2nd level (line) for light blue.

The COLOR signal (from the VIC-II) can be found at U7, Pin 14.

The COLOR signal is generated by the VIC-II

This is the COLOR (Burst). It is not easy to get it steady on the scope display.

The Composite Video signal is generated in the RF modulator and can be probed at the ferrite bead FB2.

The composite video signal. It contains both, the luminance and the chrominance (color) information

The (S-Video) Luminance is generated in the RF modulator and can be probed at FB3.

Luminance

The (S-Video) Chrominance is also generated in the RF modulator and can be probed at FB4.

Chrominance

The Interrupts
The interrupts are signals that let the CPU branch from normal execution to special interrupt routines. They are generated by the peripheral chips CIA1, VIC-II or a cartridge in the extension port.

/IRQ can be probed at U6, Pin 3.

The settings:
Coupling = DC
Trigger= rising edge
Time = 2ms/DIV
Voltage = 2V/DIV

/IRQ

/IRQ is active LOW. A pulse is issued by the CIA1 about every 1/60 second. I assume, that this is the tick for the TI (1/60s) counter.

/NMI can be probed at U6, Pin 4.It is usually HIGH.

/NMI